In today’s highly complex System-on-Chip (SoC) design, engineers face a perpetual dilemma: how to achieve the right verification at the right time and with the right accuracy? The answer lies inMixed-Abstract Modeling— a core methodology that makes modern chip design possible.No single level of abstraction can simultaneously meet all requirements in terms of efficiency, accuracy, and capacity, whether it is for smartphone processors, autonomous vehicle computing units, or AI acceleration chips. This article systematically analyzes the complete modeling hierarchy from algorithms to GDSII, using Synopsys’ DDR PHY IP as a practical example to reveal the efficient verification strategies of top chip design teams.
1. Abstraction Levels in Chip Modeling (From High to Low)
We can imagine the abstraction levels as a pyramid, where the simulation speed decreases from top to bottom, but the accuracy and level of detail increase.
2. Mixed Modeling Practice Using Synopsys DDR PHY IP as an Example
When Synopsys delivers its DDR PHY IP, it does not just provide a GDSII layout file. It offers a complete set of models at different abstraction levels to meet the needs of various roles and stages within downstream SoC design teams.When an SoC team integrates Synopsys DDR PHY, they will use different models at different stages, and evenmix them in the same simulation.Scenario: SoC Team Integrating Synopsys DDR PHY
1. Stage One: Architecture Exploration and Software Development (Using TLM Model)
- SoC Team Needs: Start system bus performance evaluation and firmware (FW) development ahead of chip RTL completion.
- Models Provided by Synopsys: TLM model of DDR PHY (usually written in SystemC).
- ❓ How to Mix Modeling:
- ✅ CPU Subsystem: May use ARM’s Cycle Models or RTL.
- ✅ Memory Controller (MC): Uses its own RTL.
- ✅ DDR PHY: Uses the TLM model provided by Synopsys.
- ✅ Memory Behavior: Uses Synopsys’ Memory Model.
- 💡 Benefits: Simulation speed is extremely fast (in MHz), allowing software engineers to debug complex firmware such as DDR initialization training processes and read/write tests on this platform without waiting for slow PHY RTL simulations.
2. Stage Two: Chip-Level Functional Verification (Using QTM or RTL Model)
- SoC Team Needs: Requires precise verification of the DFI interface timing between PHY and MC, as well as the correctness of the PHY.
- Models Provided by Synopsys: QTM model or RTL of DDR PHY.
- QTM: A model that is between TLM and RTL. It is slower than TLM but faster than RTL, providingcycle-accurate behavior without concern for gate-level delays.
- ❓ How to Mix Modeling:
- ✅ Other parts of the entire SoC may already be RTL.
- ✅ Integrate the PHY’s RTL or QTM model for full-chip simulation.
- ✅ Verification engineers will write test cases to check if the signals on the DFI interface meet protocol requirements (such as tPHY_WRLAT, tPHY_RDLAT, etc.).
- 💡 Benefits: QTM provides faster simulation speed than pure RTL while ensuring a certain level of accuracy, making full-chip simulation verification possible.
3. Stage Three: Physical Implementation and Sign-off (Using Timing Netlist and LIB)
- SoC Team Needs: Perform layout and routing (P&R), static timing analysis (STA), and power analysis.
- Models Provided by Synopsys:
- LIB File: Contains timing, power, and area information for all standard cells and macros within the PHY.
- LEF File: Contains the physical profile, pin locations, and blockage area information of the PHY.
- Gate-Level Netlist with Timing Information: Used for overall timing analysis of the SoC.
- ❓ How to “Mix”: At this point, it is no longer simulation but integration of the toolchain. The SoC’s layout and routing tools will embed the PHY’s LEF and GDSII as ahard macro into the top-level layout of the chip and use LIB and netlist for timing verification.
Conclusion: The Value of Mixed-Abstract Modeling
Using Synopsys DDR PHY as an example, we can see that the core idea of mixed-abstract modeling is:Using the correct level of abstraction model at the right time for the right purpose.
- For IP Suppliers (Synopsys): Providing a full-stack model reflects their commercial competitiveness and helps customers successfully integrate, lowering the barriers.
- For SoC Design Teams:
- 1️⃣ Significantly shorten development cycles: Achieve “Shift-Left” by allowing software and system verification to occur earlier.
- 2️⃣ Optimize resource allocation: Use fast models for exploration at higher levels and precise models for sign-off at lower levels, saving a lot of computational resources and time.
- 3️⃣ Reduce risks: By exposing system architecture issues early on virtual prototypes, catastrophic consequences of discovering errors only after tape-out are avoided.
This approach is the only feasible way to tackle today’s billion-gate complex SoC designs and is a core concept that every senior chip engineer must understand.