Not Just Booting! The Four Major Innovations of NOR Flash Technology Reshaping the Future

Part One: The Resurgence of the Stealth Hero: Why NOR Flash is “Sexy Again”

1.1 Introduction: Reassessing the “King of Code”

For a long time, under the dazzling halo of high-capacity NAND Flash, NOR Flash has seemed to play a low-key supporting role. However, this perception is rapidly changing. The core advantage of NOR Flash—its unique parallel architecture—gives it characteristics that NAND cannot match: extremely low read latency and fast random access capabilities.

This architecture is the fundamental reason why NOR Flash is unshakeable in the field of “Execute-in-Place” (XIP). Systems (such as automobiles, routers, or IoT devices) can boot and run code directly from NOR Flash without first copying it to RAM, granting the system instant boot capabilities.

As industry observers say, NOR Flash is “Sexy Again!” This resurgence is not only due to its importance in traditional boot functions but also because it is evolving into a key enabler for solving core challenges of next-generation technologies (such as artificial intelligence and autonomous driving).

1.2 Innovation Catalyst: The “28nm Wall”

The technological revolution of NOR Flash did not come from nowhere; it stemmed from a profound industry crisis: planar (2D) NOR Flash technology encountered an insurmountable “high wall” at the 28nm process node.

This crisis is rooted in a dual dilemma of technology and economics:

Cost Control: Further shrinking the process (below 28nm) requires increasingly complex and expensive photomask processes, leading to a sharp rise in costs and a complete loss of return on investment (ROI).
Physical Limits: Below 28nm, NOR Flash faces severe physical challenges in scaling drain voltage, gate length, and tunnel oxide thickness.
Integration Issues: Most critically, traditional planar embedded flash (eFlash) technology “cannot be integrated with FinFET transistor processes.” FinFET is the standard architecture for advanced logic chips (such as MCUs and SoCs) below 28nm.

Currently, while the 65nm process node remains the main revenue source in the market, 45nm and 55nm are still the mainstream processes for major suppliers (such as Macronix), the traditional scaling path to 28nm and beyond has been blocked.

However, this “28nm wall” did not end NOR Flash; instead, it became a “liberator” and “catalyst” for its technological evolution. It forced the industry to stop the singular approach of “scaling down” on a two-dimensional plane and instead opened four distinct, parallel dimensions of innovation:

Scaling Up: Breakthroughs in 3D architecture.
Scaling Smart: Applications of Compute-in-Memory (CIM).
Scaling Safe: Achieving automotive functional safety (ASIL).
Scaling Out: Advanced heterogeneous integrated packaging.

1.3 New Demand Engine: Why the Market Needs Better NOR

The significance of the “28nm wall” lies in the explosive growth of market demand for NOR Flash:

Automotive Electronics: Advanced Driver Assistance Systems (ADAS), digital cockpits, domain controllers, and in-vehicle networks are driving the demand for high-capacity, ultra-reliable NOR Flash.
Internet of Things (IoT): Billions of IoT devices require secure, low-power, and highly reliable code storage solutions.
Edge AI: The application of artificial intelligence at the endpoint (such as AIPC and AI wearables) has created a new “von Neumann bottleneck,” which provides a new opportunity for NOR Flash.

To establish a clear foundational understanding before delving into new technologies, the following table summarizes the key differences between NOR and NAND in 2024-2025:

Table 1: Key Feature Comparison of Modern NOR Flash and NAND Flash

Feature	NOR Flash	NAND Flash
Circuit Architecture	Parallel Architecture	Serial Architecture
Data Access	Fast Random Access (Byte-Level)	Serial Page/Block Access
Read Speed	Extremely Fast, Low Latency	Slower, Higher Latency
Write/Erase	Slower (Block Erase, Byte Write)
Density and Cost	Lower Density, Higher Cost per Bit	Very High Density, Lower Cost per Bit
Reliability	High Durability, Long Data Retention	Relatively Lower Durability
Core Applications	Code Storage, XIP (Execute-in-Place), System Boot

Part Two: Cutting Edge Innovation (I) — 3D Breakthrough (Breaking the Density Barrier)

2.1 Challenge: The “4Gb Code + Data” Dilemma

As automotive digital cockpits and ADAS systems become increasingly complex, they must not only store critical boot code but also vast amounts of graphics, maps, and data. This has led to a skyrocketing demand for NOR Flash capacity, quickly surpassing the 2Gb limit of 2D planar technology.

The traditional solution has been “stacking.” For example, to manufacture a 4Gb 2D NOR chip, it requires stacking up to 8 bare chips of 512Mb within a single package. This solution is not only costly but also economically unfeasible. The market urgently needs a more cost-effective single-chip high-capacity solution.

2.2 Solution: Macronix’s 3D NOR Revolution

In the face of this challenge, industry leader Macronix has taken the lead in providing an answer. At events such as the 2024 electronica exhibition, Macronix officially launched the world’s first 3D NOR Flash technology.

This is a groundbreaking breakthrough. It marks the official transition of NOR Flash from the 2D era to the 3D era. Macronix leveraged its mature 3D NAND technology experience to develop a true 3D NOR process, rather than simply stacking bare chips. This technology successfully breaks the capacity bottleneck of 2D planar technology, achieving single-chip capacities of 4Gb and even 8Gb, with plans for a roadmap of 32 layers and beyond.

2.3 In-Depth Analysis: 3D NOR Architecture (and Its Differences from 3D NAND)

The architecture of 3D NOR is key to understanding this technology. It is distinctly different from the vertical channel architecture of 3D NAND. Macronix’s solution is a “3D AND” architecture.

The implementation is roughly as follows:

First, multiple layers of oxide and nitride films are stacked on the wafer.
Then, holes are etched into these stacked layers.
Finally, the so-called “plugs” are filled into the holes, which serve as channels connecting the source and drain.

The ultimate goal of this ingenious design is to achieve a density seven times higher than 2D NOR while fully retaining the core advantages of NOR Flash: up to 100,000 programming/erase cycles and automotive-grade reliability compliant with AEC-Q100 and ASIL-B standards.

2.4 Market Impact and Strategic Divergence

Macronix’s push in 3D NOR demonstrates a significant strategic game. By 2025, among the “Big Four” in NOR Flash (Macronix, Infineon, GigaDevice, Winbond), only Macronix has invested heavily in the 3D NOR technology path.

This reveals a major strategic divergence in the industry following the “28nm wall.” Macronix’s bet is: “Density” will be the key to winning the next generation NOR market. They believe that by providing high-density, high-reliability, and cost-effective single-chip solutions through “scaling up,” they can completely conquer the automotive market, which is extremely thirsty for both code and data capacity. While competitors are pondering how to make NOR smarter or safer, Macronix has chosen to initiate a revolution at the most fundamental “process” level.

Part Three: Cutting Edge Innovation (II) — AI Revolution (From Storage to Computing)

3.1 Challenge: The “Von Neumann Bottleneck” at the Edge

As another evolutionary path of NOR Flash turns towards edge AI, it faces a completely different problem—the “Von Neumann Bottleneck.”

In traditional computing architectures, processors (CPU/GPU) and memory (Memory) are separate. During AI computations, the processor needs to frequently fetch data (weights) from memory (such as NOR Flash) and write back after calculations. This data transfer process:

Consumes enormous energy: The energy consumed in data transfer can be 10 to 100 times that of the logical operations themselves.
Creates physical bottlenecks: Bus bandwidth limits data throughput.

For battery-powered edge devices (such as smartwatches, headphones, and sensors), this energy waste is unacceptable.

3.2 Solution: NOR Flash Transforms into a “Compute Unit” (CIM)

To break this bottleneck, “Compute-in-Memory” (CIM) or “Processing-in-Memory” (PIM) technology has emerged. The core idea is: No longer transporting data, but executing AI computations directly within the memory array.

NOR Flash, especially mature “Split-Gate” NOR Flash (such as Microchip/SST’s SuperFlash® technology), is considered an ideal candidate for achieving CIM due to its high density, low power consumption, and technological maturity.

3.3 In-Depth Analysis 1: Analog CIM (High-Density Computing Engine)

The most notable NOR CIM solution currently is based on “analog computing.” Its cleverness lies in utilizing “Multi-Level Cell” (MLC) technology.

Basic Principle: A single MLC storage cell can store multiple bits (e.g., 2-bit or 3-bit) by controlling the amount of internal charge.
AI’s “Trick”: We can use different “analog” charge levels of MLC cells to represent “synaptic weights” in artificial neural networks.
Computational Process (VMM): The core operation of AI—”Vector Matrix Multiplication”—is completed instantaneously in the analog domain:

Weights (W): Stored in the analog charge levels of floating gates.
Inputs (X): Applied as analog voltage to the “word lines” of the storage cells.
Multiplication (W*X): Automatically completed through the physical properties of the storage cells (Ohm’s Law/Kirchhoff’s Law).
Summation (Σ): Achieved by aggregating the total current on the “bit line.”

This analog CIM architecture, studied at 65nm and 40nm process nodes, has demonstrated extremely high energy efficiency (e.g., 35.6 TOPS/W).

3.4 In-Depth Analysis 2: Analog CIM vs. Digital CIM (The Great Trade-off)

However, analog CIM is not without its flaws. In the NOR CIM field, a battle over “analog” versus “digital” is underway.

Challenges of Analog CIM: Although analog CIM has extremely high density and energy efficiency, it is inherently “fragile.” It is highly susceptible to noise from analog circuits and process variations, and relies on costly digital-to-analog/analog-to-digital converters (DAC/ADC), leading to “precision loss” in AI computations.
The Rise of Digital CIM: As a countermeasure, researchers have proposed “Digital Non-Volatile CIM” (DNV-CIM). This solution uses standard, more reliable “Single-Level Cell” (SLC) NOR Flash to store AI weights in a *digital lookup table (LUT)* and employs integrated digital adders for computation.
Trade-off: Digital CIM avoids the analog noise issues by operating in the digital domain, achieving higher computational precision. However, it may require more peripheral circuitry, thus “reducing storage density”.

This is not a matter of “who is right or wrong” but a typical engineering trade-off: whether to choose the extreme energy efficiency and density of the analog solution or the ultra-high precision and reliability of the digital solution? This also provides differentiated choices for downstream AIoT product designers.

3.5 Technology Spotlight: Microchip/SST’s SuperFlash® and memBrain™

The pioneers turning theory into reality are Microchip and its subsidiary SST. Their memBrain™ technology is a successfully commercialized solution that utilizes SST’s mature SuperFlash® NOR technology to achieve **analog in-memory computing**.

memBrain™ is optimized for executing VMM operations of neural networks, aiming to accelerate edge AI/ML inference. It is not just a laboratory concept but has been successfully applied to solve real-world problems, such as enabling real-time voice processing in ultra-low-power devices.

Part Four: Cutting Edge Innovation (III) — The Automotive Gold Standard (Uncompromising Safety)

4.1 Challenge: When “Reboot” is No Longer an Option

The third evolutionary path of NOR Flash leads to one of the highest value and most demanding fields: automotive electronics. In smart vehicles, NOR Flash stores the “lifeline” code for ADAS, domain controllers, gateways, and digital cockpits.

In these “safety-critical” systems, memory failures are no longer an inconvenience like a smartphone crash but can lead to catastrophic consequences. Therefore, the market has created a new hard threshold: compliance with the ISO 26262 automotive functional safety standard.

4.2 Solution: Competing for ASIL-D Certification

The ISO 26262 standard defines the “Automotive Safety Integrity Level” (ASIL), ranging from A (lowest) to D (highest). ASIL-D is the highest level of this standard, representing the most stringent and demanding safety requirements.

Achieving ASIL-D certification is rapidly becoming the “ticket to entry” in the high-end automotive NOR Flash market, sparking a “safety arms race” among industry giants.

The timeline clearly illustrates the intensity of this competition:

December 2024: GigaDevice announces that its GD25/55 series SPI NOR Flash automotive products have passed ISO 26262 ASIL-D certification.
May 2025: Just five months later, Infineon announces that its entire SEMPERE™ NOR Flash product line has received ASIL-D certification.

This rapid and heated competition indicates that automotive OEMs are making ASIL-D a mandatory requirement. Suppliers must meet this standard to “lock in” long-term design solutions (Socket) from automotive manufacturers, ensuring that memory does not need to be replaced throughout the vehicle’s lifecycle.

4.3 Technology Spotlight 1: Infineon’s SEMPERE™ “Safety Architecture”

ASIL-D certification is not just a sticker; it is backed by a complete and robust safety architecture. Infineon’s SEMPERE™ series exemplifies this architecture:

Endurance Flex Architecture: This is a key flexible design. Users can configure memory partitions to switch between “high endurance mode” (supporting over 1 million erase cycles) and “long data retention mode” (supporting up to 25 years of data retention).
Built-in Diagnostics: Includes “SafeBoot” and error-checking functions to ensure the system always operates in a safe and reliable state.
Data Integrity: The chip integrates an ECC (SECDED, Single Error Correction Double Error Detection) engine and CRC (Cyclic Redundancy Check) protection. This not only protects data in the storage array but also safeguards data transmitted between the chip and the main controller.
Core Technology: All of this is built on Infineon’s proprietary MIRRORBIT™ (2 bits per cell) high-density technology.

4.4 Technology Spotlight 2: GigaDevice GD25/55 “Challenger”

As the second-largest supplier in the global NOR Flash market, GigaDevice’s ASIL-D certification (GD25/55 series) is of great significance. It demonstrates that its automotive-grade chip design and reliability have reached world-class levels, making it a core supplier for critical applications such as ADAS.

This achievement is also part of its broader strategy: GigaDevice is simultaneously advancing on two fronts. On one hand, it aggressively enters the high-threshold industrial and automotive markets through ASIL-D certification; on the other hand, it actively positions itself in emerging consumer markets for “edge AI” such as AIPC, AI glasses, and AI wearables.

Part Five: Cutting Edge Innovation (IV) — Integration Revolution (The Future Lies in Stacking)

5.1 Challenge: The End of the “One Chip Fits All” Era

The fourth evolutionary path of NOR Flash aims to address a fundamental system integration challenge: modern systems require three different memory characteristics:

Fast code execution for instant booting (the strength of NOR).
Large capacity storage for data (the strength of NAND).
Ultra-high bandwidth for AI computations.

No single chip technology can economically and efficiently meet all three demands simultaneously.

5.2 Solution: Winbond’s Advanced Packaging Strategy

In this integration revolution, Winbond is leading the trend through its innovations in advanced packaging.

5.3 In-Depth Analysis 1: SpiStack® (Heterogeneous Stacking)

Technical Concept: Since systems need both NOR and NAND, why not package them in “one chip”?
Implementation: SpiStack® is a “stacked die” technology that can heterogeneously stack NOR Flash bare chips and NAND Flash bare chips within a single package.
Core Advantage: This solution provides a “best of both worlds” experience. System designers can continue to use their familiar, highly reliable NOR interface to boot and run code while also gaining the large capacity and fast programming/erase capabilities provided by NAND for data storage and OTA (over-the-air upgrades).

The emergence of SpiStack® reveals another interesting competitive route within the industry. To solve the “code + data” storage dilemma, Macronix (in Part Two) chose a high-investment, high-difficulty “process revolution” (3D NOR); while Winbond opted for a more pragmatic and flexible “packaging revolution” (SpiStack®). Winbond’s solution leverages existing, mature, low-cost 2D bare chips to achieve functional integration through advanced packaging, which may have significant advantages in time-to-market and cost control.

5.4 In-Depth Analysis 2: CUBE (AI-Oriented Heterogeneous Integration)

If SpiStack® is Winbond’s present, then CUBE represents its next-generation AI strategy for the future.

Technical Concept: CUBE (Customized Ultra-High Bandwidth) refers to “customized ultra-high bandwidth components”.
Implementation: This is no longer a simple stacked die but a true 3D integration platform. It utilizes:

TSV (Through-Silicon Via): Establishing vertical, shortest electrical connections between chips.
Ultra-High Bandwidth: TSV technology allows bandwidth to soar to astonishing levels of 32GB/s to 256GB/s, which is precisely what AI computing demands.
Advanced Process: CUBE is based on a 20nm process and plans to transition to 16nm by 2025.

The ecosystem of CUBE more profoundly reveals the future trends of the industry: The competition for next-generation memory is a competition of ecosystems and integration.

Winbond’s CUBE project collaborates with the entire industry chain: it unites UMC (responsible for wafer foundry), ASE, and PTI (responsible for packaging and testing) as well as Cadence (responsible for the EDA toolchain). This demonstrates that the future “memory” for AI is no longer an isolated chip but a “system” that integrates logic units and storage units through 3D heterogeneous integration. Winbond’s proposed “3DCaaS” (3D Chip as a Service) concept marks a shift in the industry from “selling chips” to “selling integrated solutions” as a business model.

Part Six: Competitive Horizon: MRAM and RRAM — Complement or Kill?

6.1 The Emergence of the “NOR Killer”

As NOR Flash continues to thrive, two powerful challengers have emerged: MRAM (Magnetoresistive Random Access Memory) and RRAM (Resistive Random Access Memory).

Their Core Advantages: MRAM and RRAM are seen as the perfect answers to the “28nm wall.” They are compatible with advanced FinFET processes and can easily scale down to 28nm or even below, which traditional embedded NOR (eFlash) cannot achieve.

6.2 The Two NOR Stories (Key Differences)

So, will MRAM and RRAM “kill” NOR Flash? The answer is: No. But they will “kill” specific types of NOR Flash.

This is the most subtle and crucial point in understanding the current memory landscape. The “NOR Flash” market has effectively split into two distinctly different battlefields:

Battlefield One: Embedded Flash (eFlash)

Definition: Storage units integrated on the same die as the MCU or SoC.
Dilemma: As mentioned earlier, it cannot be integrated with FinFET processes below 28nm.
Challengers: MRAM and RRAM are replacing eFlash on this battlefield. They are being integrated as embedded code/cache storage in the most advanced SoCs.

Battlefield Two: Discrete NOR Flash

Definition: As an independent chip connected to the main controller via interfaces such as SPI.
Evolution: All four major innovations mentioned earlier—3D NOR, ASIL-D safety architecture, SpiStack® stacking—have occurred on this battlefield.
Conclusion: MRAM/RRAM are not “NOR killers” but “eFlash killers.” They are replacing embedded NOR, while the discrete NOR market is thriving on a completely parallel track through density, safety, and integration innovations.

The following table summarizes this new competitive landscape of non-volatile memory (NVM):

Table 2: Comparison of New Technology Landscape in Non-Volatile Memory (NVM)

Technology	2D NOR (Discrete)	3D NOR (Discrete)	eMRAM (Embedded)	eRRAM (Embedded)
Process Node	Mature (e.g., 65/45nm)	Based on Mature Process Stacking	Advanced (<28nm)	Advanced (<28nm)
Scalability	Blocked at 28nm	Vertical Stacking	Scalable to <28nm	Scalable to <28nm
Core Advantages	XIP, High Reliability	Extremely High Density, Low Cost/Bit	High Durability, FinFET Compatible	Low Cost, High Density
Main Applications	Discrete Code Storage	Discrete Code + Data Storage	Embedded Code/Cache	Embedded Storage

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Part Seven: Conclusion — 2025 Outlook and the Strategy of the “Big Four”

7.1 The New Face of NOR: From “Standard” to “Specialization”

In summary, the seemingly insurmountable “28nm wall” did not become the endpoint for NOR Flash; rather, it became the starting point for its diversified evolution. It forced NOR Flash to break free from a singular, commoditized scaling path and differentiate into four distinct, value-multiplying “specialization” paths:

The 3D Path: Solving the high-density code and data storage dilemma (Part Two).
The AI Path: Becoming an intelligent in-memory computing unit (Part Three).
The Safety Path: Serving as the “lifeline” for automotive and industrial applications (Part Four).
The Integration Path: Acting as a high-bandwidth “component” for advanced AI systems (Part Five).

The future of NOR Flash is no longer a “one-size-fits-all” solution but a diversified, specialized, and exciting new domain.

7.2 The Strategic Chessboard of the “Big Four” in 2025

For industry observers, the most exciting part of this technological revolution lies in the fact that the four leading manufacturers have chosen completely different evolutionary paths based on their respective strengths. The following table summarizes the strategic overview based on the latest developments in 2024-2025, serving as the ultimate guide to understanding the future landscape of NOR Flash.

Table 3: 2025 NOR Flash “Big Four” Strategic Overview

Manufacturer	Key Technology in 2025	Strategic Focus and Market Approach
Macronix	3D NOR Flash	Density Champion. Betting on “scaling up” to win the data surge in the automotive and high-end markets with revolutionary 3D processes and single-chip high-density solutions.
Infineon	SEMPER™ (ASIL-D Certification)	Safety Leader. Betting on “scaling safe” to lock in long-lifecycle automotive and industrial critical applications (Socket) with top-tier functional safety architecture.
GigaDevice	ASIL-D Certification / Edge AI Layout	Agile Challenger. Betting on “fast follow and expand,” matching top automotive safety standards while actively seizing emerging consumer AI markets such as AIPC.
Winbond	CUBE (3D Integration) / SpiStack®	Integration Innovator. Betting on “collaborative scaling” to provide high-bandwidth, customized “solutions” for cutting-edge edge AI systems through advanced packaging and heterogeneous integration rather than just “chips”.