Low Power Design in Embedded Systems

Abstract

This article briefly describes the main classifications and sources of power consumption in embedded systems, as well as how to achieve low power design from both software and hardware perspectives. The low power design methods mentioned in this article are relatively simple, as the most critical parts of instruction cache and data cache are briefly skipped due to their complexity and abstraction. Those interested in this area can refer directly to papers related to instruction storage and data storage.

Characteristics

Compared to general systems, embedded systems have different characteristics in terms of power consumption.

First, the software and hardware of embedded systems are designed separately based on specific scenarios, such as multimedia consumer devices, industrial applications, aerospace, military, etc. The characteristics vary widely, requiring different hardware architectures to optimally balance performance and cost based on the expected goals of the target application. Secondly, unlike general systems, embedded systems are characterized by limited resources and low energy budgets. The use of integrated power sources (such as batteries) limits their operating time when not connected to a power supply. Thirdly, to ensure reliability and predictability, embedded systems provide high computational power to meet the real-time requirements of various system tasks.

The small size of embedded systems limits the manageable amount of heat dissipation, generally resulting in poor heat dissipation. When the overall power is too high, it can lead to system overheating. Statistics show that for every 15-degree increase, the failure rate of devices doubles. This characteristic is crucial for special systems such as medical devices. Additionally, some medical embedded systems come into contact with the human body or are directly implanted, and even a slight increase in temperature can affect the human body, which raises higher requirements for system power consumption.

Power Consumption Classification

Think about it, disregarding the abstract software, when an embedded system is running, it is essentially powered by a power source driving a crystal oscillator to generate a clock, and then various transistors inside the chip continuously flip under the influence of the clock signal, combining to produce various logic, and then driving peripherals to work. Ultimately, electrical energy is gradually consumed by these dynamic changes and static components.

Therefore, the power consumption of embedded systems can be roughly divided into two categories: dynamic power consumption and static power consumption. Dynamic power consumption is generated by the charging and discharging of load capacitance and the flipping of transistors, while leakage power consumption is caused by leakage current that flows even when the device is in an inactive state. Dynamic behavior can be seen as data computation, while static behavior can be seen as data storage. A typical embedded hardware system consists of an instruction set processor core, data cache, SRAM, DRAM, etc., and the distribution of data computation and storage is shown in the figure below.

According to professionals, the power consumption of each part varies, as shown in the figure below, where the most significant power consumption is in the instruction storage architecture (<span>IMO: Instruction Memory Organization</span>) and data storage architecture (<span>DMH: Data Memory Hierarchy</span>), which together account for nearly 70% of the total, as fetching instructions and data from external storage consumes a lot of energy.

Therefore, many experts focus on improving the hit rate of instruction and data caches to reduce system power consumption. There are numerous papers on these two aspects, filled with formulas and diagrams, but as a small embedded software engineer, I am not at that level yet and do not wish to delve into such deep topics. Interested parties can explore further.

Low Power Design

Core Ideas of Low Power Design

• Hardware aspects outside the chip:
• Reduce voltage, as long as it can drive the system to work normally and prevent performance degradation or loss due to voltage fluctuations.
• When certain functions are not needed, turn off the corresponding hardware power supply.
• Software aspects inside the chip:
• Perform as few calculations as possible in a given time, enter low power mode when there is no computational demand, and sleep more while working less.

Power Consumption Evaluation

Any design requires a standard system for evaluation. So how do we evaluate power consumption design?

Power Consumption: This is the most direct measure, referring to the total energy consumed by the circuit or system during operation. It can be assessed through static power consumption (energy consumed even when no operations are performed, mainly caused by leakage current) and dynamic power consumption (energy consumption related to circuit state transitions).

Performance per Watt: This metric reflects the performance of the system under unit power consumption. For many applications, especially in mobile devices and high-performance computing, this is a very important consideration.

Hardware Low Power Design

Partial Power Off

Using load switch chips, load switches are used to efficiently connect or disconnect the power supply to the load, achieving precise management of power supply to the load. When not needed, power supply to certain parts can be cut off, reducing both static and dynamic power consumption. This method can effectively reduce the overall power consumption of the system during standby, especially for those functional modules that are only occasionally used, such as serial ports, ADCs, Bluetooth, Wi-Fi, and other wireless communication modules or sensor components. Moreover, the energy used by these chips to switch the circuit on and off is very small. It is important to note that even if these modules are not powered on, there will still be a small amount of static loss due to the basic supply voltage.

Partial Voltage Reduction Technology

By adjusting the voltage levels of different subsystems to optimize energy efficiency, as lower operating voltages usually mean lower energy consumption, using efficient DC-DC buck converters to provide the required voltage for different circuit areas. Modern buck converters can achieve very high efficiency (over 90%), reducing energy loss caused by voltage conversion.

Software Low Power Design

Decades ago, hardware was seen as the only place to change power consumption in a system, so all low power designs focused on the hardware part. However, this paradigm has changed, as highly integrated processors rely less on external devices, and once the software logic is fixed, we can accurately predict the program’s response to specific inputs, allowing for better global optimization.

Entering Low Power Mode

Low power modes achieve energy savings by adjusting the operating state of the chip. For example, the low power modes of STM32 are described as follows:

1. Peripheral Gated Clock: In running mode, the HCLKx and PCLKx of each peripheral and memory can be stopped at any time to reduce power consumption.
2. Sleep Mode: Execute WFI (Wait For Interrupt) or WFE (Wait For Event) instructions to enter sleep mode. In this mode, only the CPU core stops running while all peripherals continue to work. The CPU can be awakened by any interrupt or event configured as a wake-up source. The overall performance is that the MCU is not executing code but retains the core registers and memory data from before sleep, and resumes execution of the instructions after WFI or WFE upon waking. There is no wake-up delay time.
3. Stop Mode: A combination of sleep mode and peripheral gated clock, all peripherals stop working, but the core’s registers and memory information are retained, so upon waking, the clock can be restored, and it can start from the original position. Note: After waking from stop mode, the system will use HSI, and if HSE is needed, additional runtime clock configuration code is required. If FLASH is set to low power mode, additional time is needed to wake up, and ADC or DAC will also consume power in stop mode.
4. Standby Mode: In standby mode, the lowest power consumption can be achieved, with the 1.2V domain powered off, and PLL, HSI oscillator, and HSE oscillator will also be turned off. Except for the backup domain (RTC registers, RTC backup registers, and backup SRAM) and registers in the standby circuit, all SRAM and register contents will be lost, and upon restart, the chip will reset, recheck boot conditions, and execute the program from the beginning.

Dynamic Voltage and Frequency Scaling (DVFS)

Automatically adjusts the processor’s voltage and frequency based on the current workload to minimize energy consumption.

1. Lower Task Frequency: For non-real-time or low computational tasks, actively reduce their operating frequency.
2. Voltage Coupling: Lowering frequency usually allows for a reduction in operating voltage (Vcore), and since power consumption is proportional to V², the energy savings from voltage reduction far exceed those from frequency reduction. The limitation of DVFS is that it can degrade performance, potentially increasing execution time or causing missed deadlines. Additionally, with the trend of using multi-core processors instead of increasing clock frequency, the benefits of DVFS are diminishing.

Task Optimization

Combine short idle intervals of tasks into a few larger idle time intervals. Larger idle intervals can reduce mode transition overhead, as the processor can remain idle or active for extended periods.

Application-Specific Memory

Map the most frequently accessed locations to small on-chip memory, as such memory is much closer to the processor, making access much less costly than accessing large off-chip memory. For example, STM32’s CCM-SRAM is directly connected to the core, providing fast, efficient, and low-power access.

Code Optimization

1. Loop Optimization: Reduce unnecessary operations within loops, such as moving invariant calculations outside the loop; use efficient data access patterns to minimize cache misses.
2. Branch Prediction Optimization: Write easily predictable conditional statements (e.g., keep if-else structures simple, place frequently accessed cases at the front in switch-case structures) to facilitate more accurate operation of the CPU’s branch predictor, reducing the overhead of pipeline flushing and reloading instructions due to prediction errors.
3. Avoid Floating Point Operations: If possible, use fixed-point numbers instead of floating-point numbers for calculations, as floating-point operations typically consume more energy than integer operations.

Algorithm Efficiency

1. Select Efficient Algorithms: Different algorithms can have significant differences in time complexity and space complexity; choosing algorithms with lower time complexity can reduce the number of instructions executed by the CPU, thereby lowering energy consumption.
2. Choice of Data Structures: Appropriate data structures can simplify algorithm logic, reducing unnecessary calculations and memory access. For example, when accessing members of a two-dimensional array, prioritize row-wise access.

Asynchronous Algorithms and Parallel Processing

1. Multithreading: Make reasonable use of multi-core processor capabilities to accelerate task completion through parallel processing, while being mindful that synchronization overhead should not offset the energy savings from performance gains.
2. Asynchronous I/O: For I/O-intensive applications, adopting an asynchronous I/O model allows the CPU to perform other tasks while waiting for I/O operations to complete, improving resource utilization.

Compiler Optimization

Using advanced compiler options, such as -O2 and -O3 optimization levels in GCC, can help generate more efficient machine code, but it is important to note that these optimizations may sometimes increase code size or alter the original program logic design.

Memory Management

1. Reduce Memory Access: Frequent memory access is one of the high-energy-consuming behaviors; optimizing data layout and access patterns can reduce unnecessary memory read and write operations.
2. Cache Friendliness: Design programs to have good cache locality, meaning that recently accessed data should remain in the cache, reducing the need to fetch data from main memory.

Tickless Mode

Tickless mode (also known as tickless operation) allows the RTOS to dynamically adjust the frequency of timer interrupts based on actual needs, rather than triggering at fixed intervals. This means that when there are no active tasks to schedule, the system can enter deeper sleep states, saving power. For example, in UCOS’s tickless mode, when setting a delay of 3 milliseconds, a clock interrupt will not occur every millisecond, but rather after 3 milliseconds.

References

• Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems A Artes, JL Ayala, J Huisken, F Catthoor – Journal of Signal Processing …, 2013 – Springer
• A Survey of Hardware Design Techniques and Issues for Energy-Efficient Embedded Systems Sparsh Mittal, Int. J. Computer Aided Engineering and Technology, Vol. 6, No. 4, 2014
• STM32F4 Chinese Reference Manual
• UCOS-III Kernel Manual