As mobile applications become increasingly prevalent and devices become lighter and thinner, issues such as CPU lag, device overheating, and battery life are becoming more common. Common methods like frequency limiting and frame dropping can degrade user experience and are not fundamental solutions. We urgently need a low-power, high-performance secret weapon to address these issues. DSPs, as already integrated resources in mobile phones, possess powerful computing capabilities and lower power consumption. In high-load application scenarios such as camera video and gaming, if fully utilized, they can significantly reduce CPU load, thereby decreasing overheating and lag.

This article mainly introduces SIMD acceleration technology based on Qualcomm’s Hexagon DSP platform, which can provide practical solutions to mobile power consumption issues.

1. Background Introduction

SIMD stands for Single Instruction Multiple Data, which is a technology that uses a single controller to control multiple processors, executing the same operation on each element of a data set (also known as a “data vector”) simultaneously, thus achieving spatial parallelism. In the image processing process, common data types for images include RGB565, RGBA8888, YUV422, etc. These formats are characterized by the fact that each component of a pixel is represented by data that is less than or equal to 8 bits. If traditional processors are used for computation, although the registers of these processors are 32-bit or 64-bit, they can only utilize their lower 8 bits for processing these data, resulting in very low efficiency. By splitting a 64-bit register into eight 8-bit registers, it can perform eight operations simultaneously, improving computational efficiency by eight times. This is the core idea behind SIMD instructions, which have gradually expanded their functionality over time.

DSP (Digital Signal Processor) is a unique microprocessor designed to process large amounts of information using digital signals. It is a dedicated processing unit optimized for data processing within SoCs from Qualcomm or MTK, known for its low power consumption and high performance. Qualcomm enhances the vector computing capabilities of its processors by introducing HVX, or Hexagon Vector eXtensions. Its efficient and powerful processing capabilities are based on SIMD technology, allowing for the parallel processing of 1024-bit data, providing advantages in video processing, AI, and other fields that require handling large amounts of data, which CPUs cannot match. Compared to powerful CPUs, DSPs excel at handling these tasks with low power consumption. As mobile usage demands continue to expand, while battery capacity is difficult to increase, effectively utilizing the low-power characteristics of DSPs can help solve issues such as overheating and lag.

Qualcomm’s Hexagon DSP leads with its unique architecture, and we will briefly introduce the Qualcomm Hexagon V66 DSP below.

2. Characteristics of cDSP Computing Components

Structural Characteristics:

The DSP includes multiple components such as cDSP (Compute DSP), aDSP (Application/Audio DSP), mDSP (Modem DSP), and lDSP (Low power DSP). Among them, cDSP is the core computing unit of the DSP, on par with the CPU in the SoC architecture, and it can access the system bus and DDR.

The main components of cDSP include:

Scalar Processor: Scalar Processor (Hexagon), generally used for logical control, supporting integer and floating-point data operations.

Vector Processor: Vector Processor (HVX/Hexagon Vector Extension), which processes vector operations;

Level 2 Cache: L2 cache, which can be used for memory acceleration in complex scenarios.

Figure 1: cDSP Architecture Diagram

The Hexagon processor includes common processing units such as XU (Execution Unit), $(Cache), RF (Register File), and MMU (Memory Management Unit). Each hardware thread contains 32 vector registers and 4 predicate registers. Each vector register is 1024 bits wide and can perform operations in word, halfword, or byte formats. Each predicate register contains 128 bits. Two vector registers can form a vector pair.

3. Instruction Introduction

By defining interfaces for upper-layer calls in the idl file, a shared object file with a .skel suffix is generated, which implements the interfaces using DSP. The FastRPC interface allows the Applications Processor to call the underlying implementation of the DSP Processor.

HVX provides various instructions such as table lookups (vlut/vscatter/vgather), shifts (vror/vasl/vasr/vlsr), and concatenation (valign/vlalign), which can be combined to achieve various functionalities.

1. Concatenation (valign/vlalign)

valign/vlalign: Removes Rt bytes from the right/left of the register and concatenates the remainder.

2. Shift (vror/vasl/vasr/vlsr)

vror: Circular right shift, treating the first and last elements of a vector as a ring, shifting right by Rt bytes.

vasl/vasr/vlsr: Logical shifts

vasr/vlsr are both right shifts, with the distinction being signed and unsigned numbers.

These can be used in multiplication and division operations, as well as in scenarios such as converting image bit depth from 10 bits to 8 bits.

3. Splitting (vshuffe/vshuffo/vshuffoe/vdeal/vshuff)

vshuffe/vshuffo: Extracts even/odd bits and places them together.

vshuffe/vshuffo: Executes two operations simultaneously, placing them separately.

vdeal collects odd/even bits and places them in two parts.

vshuff reverses the operation of vdeal, dispersing the high and low parts into odd/even bits.

4. Packing (vpacke/vpacko/vpack)

vpacke/vpacko: Can collect odd/even bits from two vectors.

vpack: Compresses two vectors into one vector, from half word to byte.

5. Table Lookup (vlut/vscatter/vgather)

vlut: Can look up a small table of 256 bytes.

vscatter/vgather can look up tables of 64kb size.

4. Algorithm Optimization Examples

Example 1: Taking the absolute value of an input matrix

Typical C++ implementation:

HVX implementation:

From the comparison above, it can be seen that HVX parallel processing can significantly reduce the number of iterations, down to one 128th of the original, greatly improving computational efficiency. The function Q6_Vh_abs_Vh() is an intrinsic interface encapsulated by HVX. You can refer to the HVX programming guide to choose appropriate instructions.

Example 2: Using L2 Cache for Acceleration

For Example 1, using L2 Cache for acceleration

Using L2 Cache to prefetch data that needs to be accessed can double the speed of memory reads.

It is important to note the following points:

1) Prefetching needs to be done in advance.

2) More than three fetch instructions may cause later fetch instructions to overwrite earlier ones if the previous ones have not completed.

3) Fetching content is relatively fast, but writing can sometimes be slow due to potential cache misses.

4) Typically, fetching below 8KB is ideal; issuing several fetch instructions can yield better results.

The use of L2 Cache can be referenced in the HVX programming guide.

Example 3: Multi-thread Optimization

HVX supports multi-threading, which requires four steps to enable:

1) prepare & check

2) prepare data and callback function

3) submit job

4) sync token job token

By reasonably distributing tasks and enabling multi-threading, the algorithm’s running time can be significantly reduced.

5. Conclusion

SIMD technology is a “data parallel” acceleration solution. When processing vector calculations, the computations between different dimensions of the same vector are independent. Compared to CPUs or GPUs, DSPs are characterized by low power consumption and high performance, providing significant advantages in handling large volumes of data and have broad application prospects in fields such as artificial intelligence and video processing. Effectively utilizing the parallel computing capabilities of DSPs can significantly offload some of the load from CPUs, thereby reducing CPU lag and overheating issues in mobile devices.

References:https://zhuanlan.zhihu.com/p/31271788https://new.qq.com/omn/20180527/20180527A099CU.htmlhttps://developer.qualcomm.com/software/hexagon-dsp-sdk/dsp-processorLong press to followKernel Craftsman WeChatLinux kernel black technology | Technical articles | Selected tutorials