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SIMD stands for Single-instruction multiple-data. It means processing multiple data points with a single instruction. This type of instruction is extremely beneficial for operations on integer arrays or pixel point operations. To support this processing mode, Intel has launched a series of technologies and instruction sets, including:
MMX technology
SSE extended instruction set
SSE2 extended instruction set
SSE3 extended instruction set
SSE3 supplementary instruction set
SSE4 extended instruction set
All technologies or instruction sets provide several instructions to support SIMD operations. The operands can be integer data or floating-point data.
For SIMD integer data operations, you can use 64-bit MMX registers or 128-bit XMM registers. For SIMD floating-point data operations, you can only use the 128-bit XMM registers.
During the Pentium II era, Intel introduced MMX technology, which includes the MMX instruction set and MMX registers. The MMX registers have a width of 64 bits and can process 8 independent byte integer operations at once, or 4 independent 16-bit integer operations, or two independent 32-bit integer operations, or one 64-bit integer operation.
By the time of the Pentium III era, Intel introduced the SSE extended instruction set. These instructions can process single-precision floating-point data in XMM registers or integer data in MMX registers. Some SSE instructions provide control over state, cache, and memory access order.SSE instruction set has been enhanced for image processing, such as 3D modeling, rendering, and video decoding.
After the launch of the Pentium 4 and Xeon series processors, SSE2 extended instruction set was added. These instructions can use the same XMM registers to process double-precision floating-point data and integer data, enhancing the capability to process 64-bit integer data. In addition, SSE2 also provides new support for cache and memory access order.
The SSE3 extended instruction set was released alongside the Pentium 4 processor’s hyper-threading technology. SSE3 added 13 new instructions to improve the performance of SIMD related operations.
The SSSE3 extended instruction set added 32 instructions to enhance the performance of SIMD for integer data operations, first used in the Intel Xeon 5100 series and Intel Core 2 processors.
The SSE4 extended instruction set added 54 instructions, of which 47 are called SSE4.1 and the remaining 7 are called SSE4.2.
Entering the Intel 64 architecture, the 128-bit XMM registers increased from 8 to 16.
Later, Intel introduced the AVX (Advanced Vector Extensions) technology. Compared to traditional SIMD related operations, AVX provides more powerful architectural support. The main features are as follows:
It provides 256-bit YMM registers to extend the original XMM registers.
Compared to the 128-bit XMM registers, it offers a twofold performance increase (if execution time is consistent).
Compared to traditional SIMD instructions, AVX instructions can support 3 operand operations, providing better flexibility for programming. If there are only two operands, the content of one operand will inevitably be replaced by the result of the operation.
Reference:
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 1 (2.2.7 SIMD Instructions)
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