Introduction to Makefile

Since we want to be able to selectively compile source files, we cannot compile all source files in one command as we did in the previous section; instead, we need to write them separately:

all: hellohello: main.o function1.o function2.o        g++ main.o function1.o function2.o -o hellomain.o: main.cpp        g++ -c main.cppfunction1.o: function1.cpp        g++ -c function1.cppfunction2.o: function2.cpp        g++ -c function2.cpp
clean:        rm -rf *.o hello

The above Makefile contains an important syntax: :. That is, target: files that the target depends on.

Following the logic in the code:

1. When you type make in the command line, it will default to execute the all target;

2. And the all target depends on hello, which does not exist in the current directory, so the program starts to read the commands below… finally finds the hello target;

3. When it is about to execute the hello target, it finds that it depends on main.o, function1.o, and function2.o, which do not exist in the current directory, so the program continues to execute;

4. When it encounters the main.o target, it depends on main.cpp. Since main.cpp exists in the current directory, it can finally compile and generate the main.o object file. The other two functions will be compiled in turn, and after all are compiled, it returns to the hello target, links various binary files, and generates the hello file.

The first time you compile, the command line will output:

g++ -c main.cppg++ -c function1.cppg++ -c function2.cppg++ main.o function1.o function2.o -o hello

This proves that all source code has been compiled. If we make a slight modification to main.cpp and then re-run make (without running make clean first), the command line will only show:

g++ -c main.cppg++ main.o function1.o function2.o -o hello

Thus, we have demonstrated the selective compilation feature of Makefile. Next, we will introduce how to declare variables in Makefile.

We want to consolidate the commands that need to be repeatedly typed into variables so that we can use the corresponding variable when needed. This way, if we need to modify these commands in the future, we can just change one line of code where they are defined.

CC = g++CFLAGS = -c -WallLFLAGS = -Wall
all: hellohello: main.o function1.o function2.o        $(CC) $(LFLAGS) main.o function1.o function2.o -o hellomain.o: main.cpp        $(CC) $(CFLAGS) main.cppfunction1.o: function1.cpp        $(CC) $(CFLAGS) function1.cppfunction2.o: function2.cpp        $(CC) $(CFLAGS) function2.cpp
clean:        rm -rf *.o hello

In the Makefile above, three variables are defined at the beginning: CC, CFLAGS, and LFLAGS. Here, CC indicates the chosen compiler (it can also be changed to gcc); CFLAGS indicates the compilation options, where -c is used in g++, and -Wall indicates that all warnings encountered during compilation will be displayed; LFLAGS indicates linking options, which do not include -c. These names are user-defined; what really matters is the content they hold, so as long as the following code correctly references them, it doesn’t matter what they are named. It is easy to see that when referencing variable names, you need to enclose them in $() to indicate that this is a variable name.

The third version of the Makefile is still not concise enough; for example, the contents of our dependencies often repeat those in the g++ command:

hello: main.o function1.o function2.o        $(CC) $(LFLAGS) main.o function1.o function2.o -o hello

We don’t want to type so much; can we make good use of : content? This introduces several special symbols (which is precisely why Makefile can seem like a foreign language and scare off many beginners):

$@ ，$<，$^

For example, we have the target: dependencies pair: all: library.cpp main.cpp

$@ refers to all, which is the target

$< refers to library.cpp, which is the first dependency

$^ refers to library.cpp and main.cpp, which are all dependencies

Therefore, the Makefile snippet at the beginning of this section can be modified to:

hello: main.o function1.o function2.o        $(CC) $(LFLAGS) $^ -o $@

And the fourth version of the Makefile looks like this:

CC = g++CFLAGS = -c -WallLFLAGS = -Wall
all: hellohello: main.o function1.o function2.o        $(CC) $(LFLAGS) $^ -o [email protected]: main.cpp        $(CC) $(CFLAGS) $<function1.o: function1.cpp        $(CC) $(CFLAGS) $<function2.o: function2.cpp        $(CC) $(CFLAGS) $<
clean:        rm -rf *.o hello

However, typing file names manually is still a bit cumbersome. Can we automatically detect all the cpp files in the directory? Additionally, since main.cpp and main.o differ only by one suffix, can we automatically generate the object file names by changing the suffix of the source file to .o?

To achieve automatic detection of cpp files and automatic replacement of file name suffixes, we need to introduce two new commands: patsubst and wildcard.

wildcard

wildcard is used to obtain file names that match specific rules, for example, the following code:

SOURCE_DIR = . # If it's the current directory, it can also be omittedSOURCE_FILE = $(wildcard $(SOURCE_DIR)/*.cpp)target:        @echo $(SOURCE_FILE)

After running make, the output will be all the .cpp files in the current directory:

./function1.cpp ./function2.cpp ./main.cpp

Where @echo before @ is to avoid command echoing. In the previous text, make clean called rm -rf, which would output this command in the terminal; if you add @ before rm, it will not be output.

patsubst

patsubst is probably short for pattern substitution. It allows you to easily change the suffix of .cpp files to .o. Its basic syntax is: $(patsubst original pattern, target pattern, file list). Run the following example:

SOURCES = main.cpp function1.cpp function2.cppOBJS = $(patsubst %.cpp, %.o, $(SOURCES))target:        @echo $(SOURCES)        @echo $(OBJS)

The output will be:

main.cpp function1.cpp function2.cppmain.o function1.o function2.o

Combining the above two commands, we can upgrade to the fifth version of Makefile:

OBJS = $(patsubst %.cpp, %.o, $(wildcard *.cpp))CC = g++CFLAGS = -c -WallLFLAGS = -Wall
all: hellohello: $(OBJS)        $(CC) $(LFLAGS) $^ -o [email protected]: main.cpp        $(CC) $(CFLAGS) $< -o [email protected]: function1.cpp        $(CC) $(CFLAGS) $< -o [email protected]: function2.cpp        $(CC) $(CFLAGS) $< -o $@
clean:        rm -rf *.o hello

However, this version of Makefile still has room for improvement. The main.o, function1.o, and function2.o all use the same template but with different names. The sixth version of Makefile will address this issue.

Sixth Version of Makefile

Here we will use Static Pattern Rule, whose syntax is:

targets: target-pattern: prereq-patterns

Where targets are no longer a single target file but a list of target files. The target-pattern indicates the characteristics of the target files. For example, if the target files all end with .o, it can be represented as %.o, and the prereq-patterns (prerequisites) indicate the characteristics of the dependency files, for example, if the dependency files all end with .cpp, it can be represented as %.cpp.

Using the above method, any element in the targets list can find its corresponding dependency file. For example, through the main.o in targets, we can lock onto main.cpp.

Here is the sixth version of the Makefile:

OBJS = $(patsubst %.cpp, %.o, $(wildcard *.cpp))CC = g++CFLAGS = -c -WallLFLAGS = -Wall
all: hellohello: $(OBJS)        $(CC) $(LFLAGS) $^ -o $@$(OBJS):%.o:%.cpp        $(CC) $(CFLAGS) $< -o $@
clean:        rm -rf *.o hello

I noticed that some Makefiles set the -lm flag, which is found to link the math library because the code may include:

#include<math.h>

For example:

g++ -o out fun.cpp -lm

CC = g++LIBS = -lmout: fun.cpp        $(CC) -o $@ $^ $(LIBS)