I looked at my article inventory, and it seems I don’t have an article about Makefile, so this one can fill that gap.
Makefile Predefined Variables
Predefined variables are system-provided variables.
| Predefined Variable | Function |
|---|---|
| AR | Name of the library file maintenance program, default is ar |
| AS | Name of the assembler program, default is as |
| CC | Name of the C compiler, default is cc |
| CXX | Name of the C++ compiler, default is g++ |
| ARFLAGS | Options for the library file maintenance program, no default value |
| ASFLAGS | Options for the assembler program, no default value |
| CFLAGS | Options for the C compiler, no default value |
| CXXFLAGS | Options for the C++ compiler, no default value |
Makefile Automatic Variables
| Automatic Variable | Function |
|---|---|
| $* | Name of the target file without the extension |
| $< | Name of the first dependency file |
| $? | All dependency files with timestamps later than the target file |
| $@ | Full name of the target file |
| $^ | All unique dependency files |
The last two are commonly used.
Makefile Implicit Rules
Automatically finds the corresponding .c file for the .o file.
No need to specify the rule for generating the .o file.
It automatically compiles the corresponding .c file when the .o file is specified.
This is very common in uboot and linux kernel.
In uboot and linux kernel, you often see include ···config.mk.
This is equivalent to including a sub-makefile; although the filename is different, it can be treated as a makefile file, and there is basically no difference between the two.
Including Other Makefiles and Nested Makefiles
Include:
include makefile filename
This expands the sub-makefile directly.
Nested:
subsystem:
cd subdir && $(MAKE)
Equivalent to:
subsystem:
$(MAKE) -C subdir
Both of the above methods have the same effect.
Makefile Management Commands
| Command | Function |
|---|---|
| -C dir | Read the makefile in the specified directory |
| -f file | Read the file in the current directory as the makefile |
| -i | Ignore all command execution errors |
| -I dir | Specify the directory where the included makefile is located |
Compilation Solutions for Too Many Source Files
Separate makefiles or hierarchical makefiles.
Solution for Multiple Output Files
-
Multiple makefile files, nested with each other -
Use the pseudo-target make all
Makefile Environment Variables
-
Ordinary variables become environment variables after being exported.
Environment variables are generally required to be UPPERCASE, while ordinary variables are lowercase.
Use export variable_name to export.
-
Using Environment Variables
Environment variables are similar to global variables shared among all makefiles in the project.
Defining an environment variable will affect other makefile files in the project, so use with caution.
Ordinary variables only take effect in the current file.
-
Built-in Environment Variables of Makefile
For example, the predefined variables mentioned above.
Passing parameters when executing the make command is also equivalent to passing an environment variable (highest priority, can override the variable values defined in the original makefile).
Makefile Wildcards
| Symbol | Function |
|---|---|
| * | Any number of arbitrary characters |
| ？ | One arbitrary character |
| [] | Matches characters in brackets sequentially, without spaces |
% represents any character, similar to *, but % is generally only used in rule descriptions, so it is also called rule wildcard.
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