Introduction to Make and Makefile in Compilation and Linking

Introduction

Many engineers without formal training are actually quite unfamiliar with the compilation and linking of projects (including the author himself). However, if we want to create our own projects or implement a project from 0 to 1, or if we want to optimize programs, modify the memory layout, or implement memory protection under the AUTOSAR architecture, knowledge of compilation and linking is essential. In the spirit of learning thoroughly, we decided to implement a compilation environment based on the AUTOSAR architecture on a Windows operating system from 0 to 1. At the same time, to improve our coding skills, we will implement a commonly used data structure library from 0 to 1. If there are excellent open-source AUTOSAR codes, we plan to include them as well. We plan to manually write the entire project’s makefile and use the make tool to compile the project directly, while also writing the CMakeLists file to support CMake in generating the makefile file for compiling the entire project.

For those unfamiliar with compilation tools, you can refer to this article: https://blog.51cto.com/xiacaojun/5648507

Introduction to Make and Makefile in Compilation and Linking

The tools we will use:

Project Build Generation Tool: CMake

Introduction to Make and Makefile in Compilation and Linking

Introduction to Make and Makefile in Compilation and Linking

Project Build Tool: make

Introduction to Make and Makefile in Compilation and Linking

Introduction to Make and Makefile in Compilation and Linking

Compiler:

Windows: gcc/g++

Introduction to Make and Makefile in Compilation and Linking

Introduction to Make and Makefile in Compilation and Linking

Introduction to Make and Makefile in Compilation and Linking

TC3xx: Green Hills (GHS)

For an introduction to installing CMake on Windows, please refer to this article: Windows CMake Beginner’s Guide (Hello World)

Contents of this article

Introduction to Make and Makefile in Compilation and Linking

Note: This article references some third-party tools and documents. If there is any infringement, please contact the author for removal!

Main Text

1.What is make

make is an application

that can parse the dependencies between source programs

automatically maintains the compilation work based on dependencies

executes various commands in the host operating system

How to understand automatically maintains the compilation work based on dependencies? When we start compiling, it starts normally, but when it encounters an error at some point during compilation, make ensures that the correctly compiled files before the error do not need to be recompiled during the next compilation.

2.What is makefile

makefile is a description file

defines a series of rules to specify the order of compilation of source files

has specific syntax rules, supports function definitions and calls

can directly integrate various commands in the operating system

3. The relationship between make and makefile

The descriptions in the makefile guide the make program on how to complete the work; make executes commands based on the rules in the makefile and ultimately completes the compilation output.

Introduction to Make and Makefile in Compilation and Linking

4.The simplest makefile example

hello:  echo "hello makefile"

hello: is the target

echo hello makefile: the command to execute to achieve the target

Note: The command after the target needs to be separated by the Tab key (β€˜ ’), not by 4 spaces!

5.Example of using make

make -f mf.txt hello

Description: Find the target using the hello keyword in the mf.txt file and execute the command at hello.

-f: tells the make tool that we are using the file following -f to find the action to execute, which is at hello.

6.Abbreviated example of make

make hello

Description: Use the hello keyword to find the makefile or Makefile file and execute the command at hello.Let make search for the target hello; if we omit -f and do not know the makefile file, it will default to look for a file named makefile or Makefile in the current directory.

make

Description: Searches for the top-level target in the makefile or Makefile file and executes the command for the top-level target.

7.Programming Example

Create a file: make.txt

Introduction to Make and Makefile in Compilation and Linking

Write to make.txt

#make.txthello:  echo "hello makefile"

Introduction to Make and Makefile in Compilation and Linking

The contents written in the makefile are very similar to a program, and make is like an interpreter, interpreting a script program.

The contents written in the makefile are a type of script program that can be interpreted and executed, with make acting as the interpreter.

Rename make.txt to makefile:

Introduction to Make and Makefile in Compilation and Linking

Modify the contents of the makefile as follows:

#makefilehello:  echo "hello makefile"
test:  echo "test"

Introduction to Make and Makefile in Compilation and Linking

8.Summary

make is just a specialized application.

make is used to execute corresponding commands based on specified targets.

makefile is used to define targets and the commands needed to achieve those targets.

makefile has specific syntax rules, supporting function definitions and calls.

References:

1. Teacher Tang’s course on DITAI software

2. Professional Embedded Software Development Books

End

γ€ŒThe Automotive Electronics Embedded series is simultaneously launched on CSDN, titled AUTOSAR Advancement Road. This series introduces each module in detail according to the actual development and maintenance processes in projects. It covers core concept introductions, actual requirement descriptions, project configurations, special requirement introductions, principles behind them, and summaries of practical engineering experiences. The goal is for readers to understand the principles after each chapter and complete a module configuration or solve a problem based on requirements.」

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