This article mainly introduces some basic knowledge about embedded systems, hoping to be helpful to everyone.
1. Definition of Embedded Systems
(1) Definition: An application-centered, computer technology-based, customizable hardware and software system that meets the strict requirements of application systems on functionality, reliability, cost, size, and power consumption.
(2) The four stages of embedded system development: no operating system stage, simple operating system stage, real-time operating system stage, and Internet-oriented stage.
(3) Intellectual Property Core (IP Core): A functional module with intellectual property rights, specific functions, standardized interfaces, and reusable in multiple integrated circuit designs, which is a fundamental component for achieving System on Chip (SoC).
(4) IP core modules have behavioral, structural, and physical design levels, which can be divided into three categories based on the description of functional behavior: soft core, firm core, and hard core.
2. Components of Embedded Systems
Includes: hardware layer, intermediate layer, system software layer, and application software layer.
(1) Hardware layer: Embedded microprocessor, memory, general device interface, and I/O interface.
Embedded core module = microprocessor + power circuit + clock circuit + memory.
Cache: Located between main memory and the embedded microprocessor core, it stores the program code and data most frequently used by the microprocessor in the recent period. Its main goal is to reduce the memory access bottleneck caused by the memory to the microprocessor core, making processing speed faster.
(2) Intermediate layer (also known as Hardware Abstraction Layer (HAL) or Board Support Package (BSP)).
It separates the upper software of the system from the lower hardware, allowing upper software developers to focus on the development based on the interfaces provided by the BSP layer without needing to know the specifics of the lower hardware.
BSP has two characteristics: hardware dependency and operating system dependency.
Designing a complete BSP requires two parts of work:
A. Hardware initialization of the embedded system and BSP functionality.
Chip-level initialization: A purely hardware initialization process that gradually sets the embedded microprocessor from its power-up default state to the operational state required by the system.
Board-level initialization: An initialization process that includes both hardware and software, establishing a runtime environment for subsequent system initialization and application programs.
System-level initialization: A software-centric initialization process that initializes the operating system.
B. Design hardware-related device drivers.
(3) System software layer: Composed of RTOS, file systems, GUI, network systems, and general component modules.
RTOS is the basis and development platform for embedded application software.
(4) Application software: Composed of applications developed based on real-time systems.
3. Real-Time Systems
(1) Definition: A system that can complete its functions and respond to external/internal, synchronous/asynchronous events within specified or determined time.
(2) Difference: General systems generally pursue average response time and user convenience; real-time systems primarily consider system behavior under worst-case scenarios.
(3) Characteristics: Time constraints, predictability, reliability, and interaction with the external environment.
(4) Hard real-time (strong real-time): Refers to applications whose timing requirements must be fully met; otherwise, significant safety accidents or major loss of life and property may occur, such as in aerospace and military applications.
(5) Soft real-time (weak real-time): Refers to applications that have timing requirements but occasional violations of these requirements do not severely impact system operation and the environment, such as monitoring systems and real-time information collection systems.
(6) Constraints on tasks include: time constraints, resource constraints, execution order constraints, and performance constraints.
4. Scheduling in Real-Time Systems
(1) Scheduling: The entire process of determining when and where each task is executed given a set of real-time tasks and system resources.
(2) Preemptive scheduling: Typically priority-driven scheduling, such as uCOS. The advantages are good real-time performance and quick response, with relatively simple scheduling algorithms that can guarantee high-priority task timing constraints; the disadvantages are frequent context switching.
(3) Non-preemptive scheduling: Typically time-slice-based scheduling that does not allow tasks to be interrupted during execution; once a task occupies the processor, it must complete execution or voluntarily relinquish it, such as in WinCE. The advantages are fewer context switches; the disadvantages are low effective resource utilization of the processor and poor schedulability.
(4) Static table-driven strategy: The system generates a runtime schedule before running based on the time constraints and relationships of each task, indicating the starting execution time and duration of each task.
(5) Priority-driven strategy: Determines the execution order of tasks based on their priority levels.
(6) Classification of real-time tasks: periodic tasks, sporadic tasks, and aperiodic tasks.
(7) General structural model of real-time systems: Data collection tasks implement the collection of sensor data, processing tasks handle the collected data, and send the processed data to the actuator management tasks for control.
5. Architecture of Embedded Microprocessors
(1) Von Neumann architecture: Programs and data share a single storage space, with program instruction storage addresses and data storage addresses pointing to different physical locations in the same memory, using a single address and data bus, with the same width for programs and data. For example: 8086, ARM7, MIPS…
(2) Harvard architecture: Programs and data are two independent memories, each with its own addressing and access, separating program storage and data storage. For example: AVR, ARM9, ARM10…
(3) Comparison of characteristics between CISC and RISC.
The time P required for a computer to execute a program can be calculated using the formula:
P = I × CPI × T
I: The number of instructions the high-level language program runs on the machine after compilation.
CPI: The average number of cycles required to execute each instruction.
T: The time for each machine cycle.
(4) The concept of pipelining: Transforming the serial execution process of an instruction in the CPU into overlapping execution of several instruction subprocesses.
(5) Pipeline metrics:
Throughput: The number of results processed by the pipeline machine in a unit time. If the subprocesses of the pipeline take different amounts of time, the throughput should be the inverse of the longest subprocess.
Establishment time: The time from when the pipeline starts working to when it reaches maximum throughput. If m subprocesses take the same time, t, then establishment time T = mt.
(6) The byte order of information storage
A. Memory unit: byte (8 bits)
B. Word length determines the addressing capability of the microprocessor, which is the size of the virtual address space.
C. The virtual address space of a 32-bit microprocessor is 2^32, or 4GB.
D. Little-endian byte order: The low byte is at the low address in memory, and the high byte is at the high address.
E. Big-endian byte order: The high byte is at the low address in memory, and the low byte is at the high address.
F. The storage order of network devices depends on the data link layer in the OSI model.
6. Basics of Logic Circuits
(1) Logic circuits are divided into combinational logic circuits and sequential logic circuits based on whether they have storage functions.
(2) Combinational logic circuits: The output of the circuit at any moment depends only on the input signals at that moment, regardless of the circuit’s state before the input signals acted. Common logic circuits include decoders and multiplexers.
(3) Sequential logic circuits: The output of the circuit at any moment depends not only on the input at that moment but also on the circuit’s state at that moment. Therefore, sequential circuits must include memory elements. Flip-flops are the basic components of sequential logic circuits. Common sequential logic circuits include registers and counters.
(4) Truth tables, Boolean algebra, De Morgan’s laws, and the concept of gate circuits.
(5) NOR (not-or) and NAND (not-and) gate circuits are called universal gate circuits and can implement any logical function.
(6) Decoder: A combinational logic network with multiple inputs and multiple outputs.
Each time an n-bit binary code is input, at most one output among m outputs is valid.
When m = 2^n, it is a full decoding; when m < 2^n, it is a partial decoding.
(7) Due to the low output current of integrated circuits at high levels and relatively larger output current at low levels, low-level driving is often used when driving LEDs with integrated gate circuits. The LCD seven-segment character display uses the different optical characteristics of liquid crystals with and without an external electric field to display characters.
(8) Clock signals are fundamental to sequential logic, determining when the state in logic units should be updated. Synchronization is a major constraint in clock-controlled systems.
(9) When selecting flip-flops, the triggering method must be considered. There are two triggering methods:
Level-triggered: With a simple structure, it is commonly used to form registers.
Edge-triggered: With strong resistance to data line interference, it is commonly used to form registers, counters, etc.
7. Bus Circuits and Signal Driving
(1) A bus is a collection of various signal lines, serving as a common path for transmitting data, addresses, and control information among components in embedded systems. At any given moment, each path can transmit one binary signal. Depending on the type of information transmitted by the bus, it can be divided into: data bus (DB), address bus (AB), and control bus (CB).
(2) Main parameters of the bus:
Bus bandwidth: The amount of data that can be transmitted on the bus in a given time, usually expressed in MByte/s.
Bus width: The number of bits that can be transmitted simultaneously by the bus, commonly referred to as 32-bit or 64-bit bus width. The wider the bus width, the greater the data transfer rate per second, thus increasing bus bandwidth.
Bus frequency: The operating clock frequency in MHz; a higher operating frequency means faster bus operation and wider bus bandwidth.
Bus bandwidth = Bus width × Bus frequency / 8, measured in MBps.
Common buses: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus, and CAN bus.
(3) Only devices with tri-state outputs can connect to the data bus; a common tri-state gate is the output buffer.
(4) When the load connected to the bus exceeds its load capacity, a buffer or driver must be added between the bus and the load, with the most common being a tri-state buffer, which serves to drive and isolate.
(5) Bus multiplexing technology allows data and address buses to share. However, it introduces two issues:
A. Additional external circuitry is needed to decouple the bus signals, such as address latches.
B. The bus speed is relatively lower than that of non-multiplexed bus systems.
(6) Two types of bus communication protocols: synchronous and asynchronous.
(7) The solution to the bus arbitration problem is based on the concept of priority.
8. Level Conversion Circuits
(1) Digital integrated circuits can be divided into two categories: bipolar integrated circuits (TTL) and metal-oxide-semiconductor (MOS).
(2) CMOS circuits are widely used due to their extremely low static power consumption, high operating speed, and strong anti-interference capability.
(3) The solution to the interface difficulties between TTL and CMOS circuits is to connect a pull-up resistor R between the TTL circuit output and the power supply, with the value of the pull-up resistor R determined by the high-level output leakage current IOH of TTL; different series of TTL should use different R values.
9. Basics of Programmable Logic Devices
In this area, having a conceptual understanding is generally sufficient.
10. Basic Information Representation and Computation in Embedded Systems
(1) Carry counting system and conversion: This is relatively simple, and one should master how to perform conversions as it may be questioned.
(2) Representation of numbers in computers: source code, one’s complement, and two’s complement.
The one’s complement of a positive number is the same as its source code, while the one’s complement of a negative number is the source code excluding the sign bit, inverted bit by bit.
The two’s complement of a positive number is the same as its source code, while the two’s complement of a negative number is the one’s complement plus one.
For example, the source code of -98: 11100010B
One’s complement: 10011101B
Two’s complement: 10011110B
(3) Fixed-point representation: The position of the decimal point is fixed by convention.
Floating-point representation: The position of the decimal point is variable, consisting of a mantissa and an exponent.
Any binary N can be expressed as: N = 2^P × S. S is the mantissa, and P is the exponent.
(4) Representation of Chinese characters: Understanding the conversion between GB2318-80 Chinese standard code and internal codes.
(5) Parameters for waveform quantization in speech encoding (there may be simple calculation problems).
Sampling frequency: The number of samples taken per second, reflecting the size of the interval between sampling points.
The upper limit of human hearing is 20kHz, so a sampling frequency above 40kHz is satisfactory.
CDs use a sampling frequency of 44.1kHz.
Measurement accuracy: The quantization levels of samples, with current standard sampling levels of 8 bits and 16 bits.
Number of channels: mono and stereo. Stereo requires twice the storage space.
11. Error Control Coding
(1) Based on the functions of code groups, they can be divided into error detection codes and error correction codes. Error detection codes can automatically detect errors, such as parity check codes; error correction codes can not only detect but also automatically correct errors, such as cyclic redundancy check codes.
(2) Parity check codes, Hamming codes, and cyclic redundancy check codes (CRC).
12. Measurement Items for Embedded Systems
(1) Performance indicators: Divided into component performance indicators and comprehensive performance indicators, mainly including: throughput, real-time performance, and various utilization rates.
(2) Reliability and safety
Reliability is the most important and prominent basic requirement for embedded systems, ensuring that an embedded system can operate normally, typically measured by the mean time between failures (MTBF).
(3) Maintainability: Generally represented by the mean time to repair (MTTR).
(4) Availability
(5) Power consumption
(6) Environmental adaptability
(7) Generality
(8) Security
(9) Confidentiality
(10) Scalability
The price in cost-performance ratio should include not only the direct purchase price of the embedded system but also installation costs, several years of operation and maintenance costs, and software rental fees.
13. Evaluation Methods for Embedded Systems: Measurement Method and Model Method
(1) The measurement method is the most direct and basic method, requiring two issues to be resolved:
A. Determine the system parameters to be measured based on the research purpose.
B. Select measurement tools and methods.
(2) Measurement methods can be divided into two types: sampling method and event tracking method.
(3) The model method is divided into analytical modeling and simulation modeling. Analytical modeling uses mathematical equations to describe the system model, while simulation modeling uses the operation of simulation programs to dynamically express the state of embedded systems for statistical analysis to derive performance indicators.
(4) The most commonly used analytical model is the queuing model, which includes three parts: input flow, queuing rules, and service entities.
(5) Evaluating a system using a model requires addressing three issues: designing the model, solving the model, and calibrating and validating the model.
Interface Technology
1. Flash Memory
(1) Flash memory is a type of non-volatile memory that can be divided into NOR Flash and NAND Flash based on structural differences.
(2) Characteristics of Flash memory:
A. Block structure: Physically divided into several independent blocks.
B. Erase before write: The write operation of Flash can only change data bits from 1 to 0, not from 0 to 1, so before writing to the memory, an erase operation must be performed to initialize the pre-written data bits to 1. The minimum unit for erase operations is a block, not a single byte.
C. Operation instructions: To perform a write operation, it must input a series of special instructions (NOR Flash) or complete a sequence of timings (NAND Flash) to write data.
D. Bit inversion: Due to the inherent characteristics of Flash, one or several data errors may occur during reading and writing. Bit inversion cannot be avoided and can only be processed afterward by other means.
E. Bad blocks: Once a block is damaged, it cannot be repaired. Operations on damaged blocks yield unpredictable results.
(3) Characteristics of NOR Flash:
Application programs can run directly in flash memory without needing to load code into system RAM. NOR Flash has high transfer efficiency, especially in small capacities from 1MB to 4MB, but its low write and erase speeds significantly affect performance.
(4) Characteristics of NAND Flash:
It can achieve very high density units, allowing for high storage density, and its write and erase speeds are also fast, which is why all USB drives use NAND Flash as the storage medium. The difficulty in applying NAND Flash lies in the need for a special system interface.
(5) Differences between NOR Flash and NAND Flash:
A. NOR Flash has slightly faster read speeds than NAND Flash.
B. NAND Flash’s erase and write speeds are significantly faster than NOR Flash.
C. NAND Flash has poor random read capabilities and is suitable for large amounts of continuous data reading.
D. NOR Flash has an SRAM interface, with sufficient address lines for easy access to each byte internally. NAND Flash shares an 8-bit bus for address, data, and commands (some products use a 16-bit bus), requiring complex I/O interfaces for serial data access during read and write operations.
E. NOR Flash typically has a smaller capacity, usually between 1MB and 8MB; NAND Flash is only used in products over 8MB. Therefore, NOR Flash is used as code storage media, while NAND Flash is suitable for data storage.
F. The maximum erase/write cycle for each block in NAND Flash is one million times, while for NOR Flash, it is one hundred thousand times.
G. NOR Flash can be connected directly like other memory and can execute code directly on it; NAND Flash requires a special I/O interface and must have a driver program written before other operations can continue. Designers must never write to bad blocks, meaning that virtual mapping must always be performed on NAND Flash.
H. NOR Flash is used in fields requiring high data reliability, such as code storage, communication products, and network processing, known as code flash memory; NAND Flash is used in fields requiring high storage capacity, such as MP3 players, storage cards, and USB drives, known as data flash memory.
2. RAM Memory
(1) Characteristics of SRAM:
SRAM stands for Static Random Access Memory, which retains a value as long as power is supplied, has no refresh cycle, and is constructed from flip-flops, resulting in low integration. Each SRAM storage unit consists of six transistors, making it costlier. It has a higher speed and is commonly used for cache memory.
Typically, SRAM has four types of pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
ADDRESS: A set of address lines.
DATA: A set of bidirectional signal lines for data transmission.
(2) Characteristics of DRAM:
DRAM stands for Dynamic Random Access Memory. It is a semiconductor memory that stores data in the form of electric charges. Each storage unit consists of a transistor and a capacitor, with data stored in the capacitor. The capacitor loses charge due to leakage, making DRAM devices unstable. It must be refreshed regularly to keep data in memory.
DRAM interfaces are relatively complex, typically having the following pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
RAS: Row address strobe signal, usually connected to the high bits of the address.
CAS: Column address strobe signal, usually connected to the low bits of the address.
ADDRESS: A set of address lines.
DATA: A set of bidirectional signal lines for data transmission.
(3) Characteristics of SDRAM:
SDRAM stands for Synchronous Dynamic Random Access Memory. Synchronous means that memory operations require a synchronized clock, with internal command sending and data transmission based on it; dynamic means that the memory array needs constant refreshing to prevent data loss. It typically operates at a main frequency of 133MHz.
(4) Characteristics of DDRAM:
DDRAM stands for Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR. DDRAM is based on SDRAM technology, where SDRAM transmits data once per clock cycle; DDR memory transmits data twice per clock cycle, once on the rising edge and once on the falling edge. At a main frequency of 133MHz, DDR memory bandwidth can reach 133×64b/8×2 = 2.1GB/s.
3. Hard Disk, Optical Disk, CF Card, SD Card
4. GPIO Principles and Structure
GPIO is the most basic form of I/O, consisting of a set of input or output pins. Some GPIO pins can be programmed to change their working direction, typically having two control registers: data register and data direction register. The data direction register sets the direction of the port. If a pin is set to output, the data register controls the state of that pin. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on the pin.
5. A/D Interface
(1) An A/D converter is a circuit that converts analog electrical quantities into digital quantities. There are many methods for implementing A/D conversion, with common methods including counting method, dual-slope method, and successive approximation method.
(2) Counting A/D conversion method
The main components of its circuit include: comparator, counter, D/A converter, and standard voltage source.
Its working principle can be summarized as follows: there is a counter that starts counting from 0, incrementing by 1 each time. Each increment serves as input to the D/A converter, generating a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, the counter continues counting until VO exceeds VIN, at which point the accumulated counter value is the output of the A/D converter.
This conversion method is simple but relatively slow, especially for higher analog voltages, making the conversion speed slower. For example, for an 8-bit A/D converter, if the input analog value is at its maximum, the counter must count from 0 to 255, performing 255 D/A conversions and voltage comparisons to complete the conversion.
(3) Dual-slope A/D conversion method
The main components of its circuit include: integrator, comparator, counter, and standard voltage source.
The working principle is that the circuit first integrates the input voltage to be measured over a fixed time, then reversely integrates it with a standard voltage at a fixed slope, returning to the starting value after a certain time. Since a fixed slope is used, the time for reverse integration to return to the starting value is proportional to the input analog voltage value; the larger the input voltage, the longer the time taken for reverse integration. By measuring the time spent on reverse integration with a standard high-frequency clock pulse, the corresponding digital quantity for the input analog voltage can be obtained, thus completing the A/D conversion.
This method has strong immunity to industrial frequency interference and high conversion accuracy, but the conversion speed is slow, typically with conversion frequencies less than 10Hz, mainly used in digital testing instruments, temperature measurements, etc.
(4) Successive approximation A/D conversion method
The main components of its circuit include: comparator, D/A converter, successive approximation register, and reference voltage source.
The working principle is essentially a binary search method, similar to the principle of using a balance scale. In A/D conversion, the D/A converter increases the conversion bit from high to low, generating different output voltages to compare the input voltage with the output voltage. First, the highest bit is set to 1, which corresponds to comparing half of the reference voltage with the input voltage; if the input voltage is less than half of the reference voltage, the highest bit is set to 0; otherwise, it is set to 1. Next, the next highest bit is set to 1, performing another binary search within half of the range, and so on, gradually approaching the value.
This method is fast, with high conversion accuracy, requiring only M clock pulses to complete the conversion for an N-bit A/D converter, making it widely used for measuring transitions that occur over tens to hundreds of microseconds.
(5) Important indicators for A/D conversion (some simple calculations may be tested):
A. Resolution: Reflecting the ability of the A/D converter to respond to minor changes in input, usually expressed in terms of the voltage level corresponding to the least significant bit (LSB) of digital output. An N-bit A/D converter can reflect 1/2^n of the full-scale analog input level.
B. Range: The range of analog input voltages that can be converted, divided into unipolar and bipolar types.
C. Conversion time: The time required to complete one A/D conversion, with its reciprocal being the conversion rate.
D. Accuracy: Accuracy and resolution are two different concepts; even with high resolution, accuracy may not be high due to reasons like temperature drift and linearity. Accuracy is expressed in two ways: absolute accuracy and relative accuracy. Absolute accuracy is often expressed as a fraction of the least significant bit (LSB) of the digital quantity, while relative accuracy is expressed as a percentage of the full-scale analog voltage.
For example, for a full-scale 10V, a 10-bit A/D chip with an absolute accuracy of ±1/2 LSB would have its minimal effective bit LSB quantization unit as: 10/1024 = 9.77mv, with an absolute accuracy of 9.77mv/2 = 4.88mv and a relative accuracy of: 0.048%.
6. Basics of D/A Interfaces
(1) D/A converters convert digital quantities into analog quantities.
(2) In integrated circuits, a T-type network is commonly used to convert digital quantities into analog currents, which are then converted into analog voltages by operational amplifiers. D/A conversion essentially requires these two stages.
(3) Classification of D/A converters:
A. Voltage output type: Commonly used as high-speed D/A converters.
B. Current output type: Generally used with external operational amplifiers.
C. Multiplicative type: Can be used as modulators and to attenuate input signals digitally.
(4) Main indicators of D/A converters: resolution, establishment time, linearity, conversion accuracy, temperature coefficient.
7. Keyboard Interface
(1) Two forms of keyboards: linear keyboards and matrix keyboards.
(2) There are two methods for recognizing closed keys on a keyboard: row scanning and column reversal.
(3) Row scanning is the common method for recognizing keys on matrix keyboards, conducted in two steps:
A. Identify which column’s key is pressed: Set all row lines to low and check whether any column line is low; if a column line is low, it indicates that a key in that column is pressed; otherwise, no key is pressed.
B. If a column has a pressed key, identify which row key is pressed: Set each row to low one by one while keeping the others high, and check for changes in the columns; if a column’s level changes to low, it confirms that the key at the intersection of that row and column has been pressed.
8. Display Interface
(1) The basic principle of LCD is to control the passage of light through different liquid crystal units by supplying power.
(2) There are two ways to provide light sources for LCDs: projection and reflection. Laptop LCD displays are projection type, with a light source behind the screen, so external light is not needed. Generally, LCDs used on microcontrollers are reflection type, requiring external light sources, relying on reflected light to operate. Electroluminescence (EL) is a method for providing light sources for liquid crystal screens.
(3) LCDs can be classified into three types based on their driving methods: Twisted Nematic (TN), Super Twisted Nematic (STN), and Thin Film Transistor (TFT).
(4) Two types of LCDs are available on the market: LCD display modules with driver circuits, which only require bus-based driving; and LCD displays without driver circuits, which use controller scanning methods.
(5) Typically, when the LCD controller operates, it requests the bus via DMA, directly reading data from a specified address (display buffer) in SDRAM, which is then converted by the LCD controller into the scan data format for the liquid crystal display.
(6) The VGA interface is essentially an analog interface, generally adopting a unified 15-pin interface, including 2 NC signals, 3 monitor data buses, 5 GND signals, 3 RGB color components, 1 horizontal sync signal, and 1 vertical sync signal. The voltage levels for color components are based on the EIA-defined RS343 standard.
9. Touch Screen Interface
(1) Touch screens can be classified into: surface acoustic wave screens, capacitive screens, resistive screens, and infrared screens based on their working principles.
(2) Touch screens are controlled using specialized chips, such as ADS7843.
10. Audio Interface
(1) Basic principle: The data input from the microphone is decoded by an audio codec to complete A/D conversion. The decoded audio data is sent to the DSP or CPU for processing via the audio controller, and then the data is sent to the audio encoder, which is converted back to analog through D/A conversion and output by the speaker.
(2) There are various formats for digital audio, with the three most common being:
A. Pulse Code Modulation (PCM): The data format used by CDs or DVDs, with a sampling frequency of 44.1kHz. At 16-bit precision, PCM audio data rate is 1.41Mb/s; at 32-bit precision, it is 2.42 Mb/s. A 700MB CD can store approximately 60 minutes of music in 16-bit PCM data format.
B. MPEG Layer 3 audio (MP3): The audio format used by MP3 players. Stereo MP3 data rates range from 112kb/s to 128kb/s.
C. ATSC digital audio compression standard (AC3): The digital audio encoding standard for digital TV, HDTV, and movies, with stereo AC3 encoded data rates of 192kb/s.
(3) IIS is a commonly used serial audio digital interface for encoding or decoding audio data. The IIS bus only handles audio data, while other control signals need to be transmitted separately. IIS uses three serial buses: data line SD, word select line WS, and clock signal line SCK.
(4) When the data field width of the receiver and sender differs, the sender does not consider the receiver’s data field width. If the sender’s data field is smaller than the system field width, zeros are padded on the low side; if the sender’s data width exceeds the receiver’s width, the excess part beyond the LSB is truncated. The field select WS is used to select left or right channels, with WS=0 indicating the left channel and WS=1 indicating the right channel. Additionally, WS allows the receiving device to store the previous byte and prepare to receive the next byte.
11. Serial Interface
(1) Serial communication refers to the transmission of data one bit at a time. Compared to parallel communication, serial communication has fewer transmission lines and lower costs, making it particularly suitable for long-distance transmission; however, it is slower.
(2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex.
(3) In terms of information format, serial communication can be divided into two types: synchronous communication and asynchronous communication.
A. Asynchronous transmission: Each character is treated as independent information for transmission, sent according to a fixed and predetermined timing, but the timing between characters is arbitrary. In asynchronous communication, characters are transmitted frame by frame, with each frame synchronized by a start bit. The interval between codes in a frame is fixed, while the time interval between adjacent frames is not fixed.
B. Synchronous transmission: In synchronous mode, not only are characters synchronized between each other, but the timing between characters remains synchronized as well. In synchronous mode, multiple characters are grouped into a character block, with 1-2 synchronization characters added before each block of information, followed by appropriate error detection data before transmission.
(4) Asynchronous communication must adhere to three regulations:
A. Character format: Start bit + data + parity bit + stop bit (the parity bit may be omitted), with low bits transmitted first.
B. Baud rate: The number of bits transmitted per second.
C. Parity bit: Odd or even parity.
a. Odd parity: The parity bit is added to ensure an odd number of 1s in the character.
b. Even parity: The parity bit is added to ensure an even number of 1s in the character.
(5) The electrical characteristics of RS-232C: negative logic.
A. On TxD and RxD: Logic 1 is -3V to -15V, and logic 0 is 3V to 15V.
B. On control lines such as TES, CTS, DTR, and DCD:
Signal valid (ON state) is 3V to 15V.
Signal invalid (OFF state) is -3V to -15V.
(6) Level conversion between TTL standards and RS-232C standards is achieved using integrated chips RS232.
(7) RS-422 serial communication interface
A. RS-422 is a unidirectional, balanced transmission specification for single machine transmission and multiple machine reception, with transmission rates up to 10Mb/s.
B. RS-422 uses differential transmission, also known as balanced transmission, using a pair of twisted wires.
C. RS-422 requires a terminal resistor, with a resistance value approximately equal to the characteristic impedance of the transmission cable.
(8) RS-485 serial bus interface
A. RS-485 is a standard established based on RS-422, adding multi-point, bidirectional communication capabilities, with communication distances ranging from tens of meters to thousands of meters.
B. RS-485 transceivers use balanced transmission and differential reception, providing the ability to suppress common-mode interference.
C. RS-485 requires two terminal resistors. For short-range transmission (under 300m), terminal resistors may not be needed.
12. Parallel Interface
(1) The data transmission rate of parallel interfaces is 8 times faster than that of serial interfaces, with a standard parallel interface data transmission rate of 1Mb/s, commonly used to connect printers, scanners, etc., hence also known as the printer port.
(2) Parallel interfaces can be divided into SPP (Standard Parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Parallel Port).
(3) Parallel buses are divided into standard and non-standard types. Common standard parallel buses include IEEE 488 bus and ANSI SCSI bus. MXI bus is a high-performance non-standard general multi-user parallel bus.
13. PCI Interface
(1) The PCI bus is a high-performance 32-bit and 64-bit bus that multiplexes addresses and data, serving as an interconnection mechanism between microprocessors and peripheral control components or additional boards.
(2) In terms of data width, PCI defines a 32-bit data bus, which can be extended to 64 bits. In terms of bus speed, there are two types: 33MHz and 66MHz.
(3) Compared to the ISA bus, the PCI bus separates the address bus and data bus in time multiplex, supporting plug-and-play, interrupt sharing, and other functions.
14. USB Interface
(1) The main features of the USB bus:
A. Simple to use, plug-and-play.
B. Each USB system has a host, and a maximum of 127 devices can be connected in this USB network.
C. Wide application range, supporting multiple devices to operate simultaneously.
D. Low-cost cables and connectors, using a unified 4-pin plug.
E. Strong error correction capability.
F. Lower protocol overhead results in higher overall bus performance, suitable for developing low-cost peripherals.
G. Supports multiple data streams and message streams between hosts and devices, accommodating both synchronous and asynchronous transmission types.
H. Bus-powered, providing 5V/100mA of power to devices.
(2) The USB system is described in three parts: USB host, USB device, and USB interconnection.
(3) The data transmission rates supported by the USB bus are three types: high-speed signaling rate of 480Mb/s; full-speed signaling rate of 12Mb/s; low-speed signaling rate of 1.5Mb/s.
(4) USB bus cables have four wires: a pair of twisted signal lines and a pair of power lines.
(5) USB is a polling bus, with the main controller initiating all data transmissions. The peripherals connected to USB share the USB bandwidth through a token-based protocol scheduled by the host.
(6) Most bus transactions involve the transmission of three packets:
A. Token packet: Indicates what transaction to perform on the bus, the USB device to be addressed, and the direction of data transfer.
B. Data packet: Transmits data or indicates that there is no data to transmit.
C. Handshake packet: Indicates whether the transmission was successful.
(7) The data transmission model between the host and device endpoints in USB is called a pipe. There are two types of pipes: stream and message. Message data has a structure defined by USB, while stream data does not.
(8) The transaction scheduling table allows flow control for certain stream pipes, using the NAK (negative acknowledgment) handshake signal to adjust the data transmission rate at the hardware level to prevent buffer overflows or underflows.
(9) The most significant feature of USB devices is plug-and-play.
(10) Working principle: When a USB device is plugged into a USB endpoint, the host communicates with the device’s endpoint 0 through the default address 0. During this process, the host issues a series of standard requests to obtain descriptors, acquiring all relevant device information to understand the device’s status and how to communicate with it. Subsequently, the host assigns a unique address to the device by issuing a Set Address request, after which the host communicates with the device using the assigned address instead of the default address 0.
15. SPI Interface
(1) SPI is a synchronous protocol interface where all transmissions refer to a common clock generated by the host, allowing the receiving external device to synchronize the reception of serial bit streams using this clock.
(2) When multiple devices are connected to the same SPI interface, the host selects the slave device through the slave’s chip select pin.
(3) SPI primarily uses four signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial Clock (SCLK), and Slave Select (CS).
(4) Both the host and slave contain a serial shift register, where the host initiates data transmission by writing a byte to its SPI serial register. The register transmits the byte to the slave via the MOSI signal line, and the slave returns its content from its shift register to the host via the MISO signal line, effectively exchanging the contents of the two shift registers.
(5) The write and read operations of the slave are completed synchronously, making SPI an efficient protocol.
(6) If only a write operation is performed, the host can ignore the received byte; conversely, if the host wants to read a byte from the slave, it must send an empty byte to trigger the slave’s transmission.
16. IIC Interface
(1) The IIC bus is a high-performance multi-master bus that features bus arbitration and synchronization between high-speed and low-speed devices.
(2) The IIC bus requires two lines: Serial Data Line (SDA) and Serial Clock Line (SCL).
(3) Each device on the bus has a unique address for identification, and each device can act as either a transmitter or receiver (depending on its function).
(4) The IIC bus has four operating modes: master transmit, master receive, slave transmit, and slave receive.
(5) During the data transmission process on the IIC bus, three types of signals are involved:
A. Start signal: SDA transitions from high to low while SCL is low.
B. Stop signal: SDA transitions from low to high while SCL is low.
C. Acknowledge signal: The receiver sends a specific low level to the sender after receiving 8 bits of data on the ninth pulse.
(6) After the master device sends a start signal, it immediately sends a slave address to notify which slave device will communicate with it. A single byte address includes 7 bits of address information and 1 bit of transmission direction indication; if the 7th bit is 0, it indicates a write operation; if it is 1, it indicates a read operation.
(7) Each byte transmitted on the SDA line is 8 bits long, with no limit on the number of bytes transmitted during each transmission. The first byte after the start signal is the address field, and each transmission byte is followed by an acknowledgment bit (ACK), with the most significant bit (MSB) of the serial data transmitted first.
(8) If the data receiver can no longer receive more data, it can interrupt the transmission by keeping SCL low, forcing the data sender to wait until SCL is released again. This allows synchronization between high-speed and low-speed devices.
(9) The working process of the IIC bus: Both SDA and SCL are bidirectional. When idle, both SDA and SCL are high. The data transmission on the IIC bus begins only when SDA becomes low, followed by SCL turning low. Each bit transmitted on the SDA line is sampled on the rising edge of SCL, and that bit must remain valid until SCL turns low again, after which the next bit is transmitted before SCL turns high again, indicating the end of data transmission.
17. Ethernet Interface
(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.
(2) Transmission encoding (06 and 07 years both): Manchester encoding and differential Manchester encoding.
A. Manchester encoding: Each bit has a level transition in the middle, with a transition from high to low representing “0” and from low to high representing “1.”
B. Differential Manchester encoding: Each bit has a level transition in the middle, using the presence or absence of a transition at the beginning of each code element to represent “0” or “1,” with a transition indicating “0” and no transition indicating “1.”
(3) In comparison, Manchester encoding is simpler, while differential Manchester encoding provides better noise suppression performance.
(4) Data transmission characteristics of Ethernet:
A. The transmission of all data bits starts with the low bit, and the bit stream is encoded using Manchester encoding.
B. Ethernet is based on a collision detection bus multiplexing method, executed automatically by hardware.
C. The transmitted data length includes destination address DA + source address SA + type field TYPE + data segment DATA + padding bits, with a minimum of 60B and a maximum of 1514B.
D. Ethernet cards can typically receive data addressed to three types of addresses: broadcast addresses, multicast addresses, and their own addresses.
E. The physical address of any two network cards is unique in the world, assigned by specialized agencies.
(5) There are two implementation methods for embedded Ethernet interfaces:
A. Embedded processor + network card chip (e.g., RTL8019AS, CS8900, etc.)
B. Processor with Ethernet interface.
(6) TCP/IP is a layered protocol consisting of: physical layer, data link layer, network layer, transport layer, and application layer. Each layer implements a specific function, corresponding to one or more transmission protocols, with each layer functioning independently of its lower layer. The protocols at each layer are as follows:
A. Application layer: BSD sockets.
B. Transport layer: TCP, UDP.
C. Network layer: IP, ARP, ICMP, IGMP
D. Data link layer: IEEE802.3 Ethernet MAC
E. Physical layer: Binary bit stream.
(7) ARP (Address Resolution Protocol)
A. The network layer uses a 32-bit address to identify different hosts (i.e., IP addresses), while the link layer uses a 48-bit physical address (MAC) to identify different Ethernet or token ring interfaces.
B. ARP function: Achieves the conversion from IP address to corresponding physical address.
(8) ICMP (Internet Control Message Protocol)
A. The IP layer uses it to exchange error messages and other important control information with other hosts or routers.
B. ICMP messages are transmitted within IP packets.
C. Network diagnostic tools ping and traceroute are actually ICMP protocols.
(9) IP (Internet Protocol)
A. IP operates at the network layer and is the core protocol of the TCP/IP protocol suite.
B. All TCP, UDP, ICMP, and IGMP data are transmitted in IP packet format.
C. TTL (Time to Live field): Specifies the lifetime of an IP packet (the number of routers the packet can pass through).
D. IP provides unreliable, connectionless packet delivery services, which are efficient and flexible.
a. Unreliable: It cannot guarantee that packets will successfully reach their destination; any required reliability must be provided by the upper layers (such as TCP). In case of an error, IP has a simple error handling algorithm—discard the packet and send an ICMP message back to the source.
b. Connectionless: IP does not maintain any state information about subsequent packets. Each packet is processed independently. IP packets can be received out of order.
(10) TCP (Transmission Control Protocol)
TCP is a connection-oriented and reliable transport layer protocol that provides high reliability end-to-end data communication between two hosts.
(11) UDP (User Datagram Protocol)
UDP is a connectionless and unreliable transport layer protocol that does not guarantee that packets will reach their destination; reliability is provided by the application layer. UDP has low overhead, making it more suitable for low-end embedded fields compared to TCP.
(12) Ports: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols; for example, the TCP port number for FTP service is always 21, for Telnet service is always 23, and for TFTP service is always 69.
18. CAN Bus Interface
(1) CAN (Controller Area Network) bus is a multi-master serial communication bus, one of the most widely used field buses internationally, initially used in electronic control networks in automotive environments. A single network formed by a CAN bus can ideally connect any number of nodes, but in practical applications, the number of nodes is limited by the electrical characteristics of the network hardware.
(2) Bus signals are transmitted using differential voltages. Two signal lines are called CAN_H and CAN_L, with static levels around 2.5V, indicating logic 1, also called