Q: What is the expected total shipment volume of Google TPU for the year 2025? How is the shipment volume distributed across the quarters?
A: The total shipment volume of Google TPU for the year 2025 is expected to reach 2.5 million units. According to quarterly cumulative data, by the end of the third quarter of 2025, the cumulative shipment volume has risen to 1.8 million units, which means that the shipment volume for the first three quarters has completed 72% of the annual target, laying a solid foundation for achieving the annual goal. Specifically, the distribution for each quarter is as follows: the first quarter has a shipment volume of about 500,000 units, which is relatively stable as the starting phase of the year; the second quarter sees a slight increase to about 550,000 units, showing a steady upward trend; the third quarter experiences significant growth, reaching about 700,000 to 750,000 units, closely related to the demand for data center deployments in the second half of the year; the fourth quarter needs to complete the remaining 700,000 to 800,000 units (2.5 million – 1.8 million) to ensure the achievement of the annual target of 2.5 million units. All these data are accurately counted based on the calendar year (calendar quarter), clearly reflecting the shipment rhythm of Google TPU throughout the year.
Q: How is the shipment volume and proportion of different models of Google TPU (V5E, V5P, V6E, V6P) distributed in 2025?
A: Among the total shipment volume of 2.5 million units of Google TPU in 2025, there are significant differences in the shipment volume and proportion of different models. The TPU V5 series (including V5E and V5P), as the current main product line, is expected to have a total shipment volume of 1.9 million units, accounting for 76% of the total annual shipment volume, making it the core support for achieving the annual shipment target. Specifically, the shipment volume of V5E is about 1.2 million units, while V5P is about 700,000 units, with a shipment ratio close to 2:1, reflecting a higher market demand for the mid-range model V5E, possibly due to its moderate performance and relatively affordable price being more suitable for most scenarios. The TPU V6 series (including V6E and V6P), as the next-generation product, is expected to have a total shipment volume of 600,000 units, accounting for 24% of the total annual shipment volume. Currently, only V6E has officially been sold in the market, taking on the initial market promotion tasks for this series; V6P is planned to be officially launched in the fourth quarter, with initial production limited due to ramp-up capacity, expected to be around 100,000 to 200,000 units, with subsequent capacity gradually increased based on market feedback.
Q: What is the shipment ratio of Google TPU in the first half versus the second half of 2025? Is there any seasonal difference?
A: The shipment ratio of Google TPU in the first half (first and second quarters) versus the second half (third and fourth quarters) of 2025 is approximately 40% and 60%, respectively, clearly reflecting a significant seasonal characteristic. From specific data, the total shipment volume in the first half is about 1.05 million units (500,000 + 550,000), while the total shipment volume in the second half is about 1.45 to 1.55 million units (700,000 to 750,000 + 700,000 to 800,000), with the second half’s shipment volume exceeding the first half by about 400,000 to 500,000 units. This significant seasonal difference mainly stems from the large-scale deployment patterns of data centers—most enterprises and institutions tend to concentrate on advancing data center construction and upgrades in the second half of the year to ensure that they meet their annual IT infrastructure investment goals by the end of the year, directly driving a surge in demand for core computing chips like TPU, resulting in a substantial increase in Google TPU shipments in the latter half of the year.
Q: What are the pricing situations for each model of Google TPU?
A: The average prices of different models of Google TPU vary due to differences in performance specifications and technical complexity, and the pricing strategy is highly aligned with product positioning. Among them, the V5E, positioned as a mid-range product focusing on cost performance, has an average price of about $3,000, making it highly competitive in scenarios where performance requirements are not extreme but cost control is emphasized; the V5P, positioned as a mid-to-high-end product with better performance, has an average price of about $6,000, which is double that of V5E, mainly targeting medium-sized data centers or AI training tasks with higher computational demands; as the first product launched in the V6 series, V6E has performance between V5E and V5P, with an average price of about $4,000, balancing performance improvement with cost control; while the V6P, planned for release in the fourth quarter, as the latest high-end product, is expected to reach a price of $8,000, primarily due to more advanced process technology, higher computational density, and new functional features. It is important to note that these prices are not completely fixed and may fluctuate slightly due to adjustments in TSMC’s process costs, but the overall change range is relatively limited, and there will not be significant price increases or decreases to maintain market price stability.
Q: What is the overall average selling price (ASP) of Google TPU in 2025? Will there be significant growth in the future?
A: The overall average selling price (ASP) of Google TPU in 2025 is expected to remain around $4,500, a price level derived from the calculation of the shipment volume proportion and unit price of each model in the V5 and V6 series—while the V5 series has a high shipment volume proportion but a relatively low unit price, the V6 series has a high unit price but a low shipment volume proportion, balancing each other to form this average price. Looking ahead to 2026, the overall ASP of Google TPU is expected to remain between $4,500 and $5,000, with no significant growth anticipated. The main reasons are twofold: on one hand, the launch of the new generation product TPU V7 series may raise the average selling price, but on the other hand, existing products like TPU V6E will gradually decrease in price as production scales up and costs are amortized, creating a counterbalance; additionally, from the perspective of market competition and customer demand, excessive price increases may affect customers’ purchasing willingness, so Google prefers to maintain price stability. Overall, the increase in ASP in 2026 is likely to be controlled at around 10%, with a relatively stable overall price trend.
Q: What is the expected revenue scale related to Google TPU in 2025? Can revenue data be split by quarter?
A: Based on the estimated sales volume and average selling price, the revenue scale related to Google TPU in 2025 is expected to reach $11.25 billion, calculated by multiplying the expected annual shipment of 2.5 million units by the overall average selling price (ASP) of $4,500. This revenue scale reflects that the TPU business has become one of Google’s important sources of income. However, currently, due to various limiting factors, it is temporarily impossible to provide precise quarterly revenue data split by individual customers or SKUs. These limiting factors include the confidentiality of customer procurement contracts, fluctuations in the shipment rhythm of different TPU models across quarters, and the difficulty of unifying internal financial statistical standards. Therefore, it is currently only possible to make rough estimates of revenue data based on the shipment ratio of 40% in the first half and 60% in the second half—i.e., approximately $4.5 billion in revenue for the first half ($11.25 billion × 40%) and approximately $6.75 billion in revenue for the second half ($11.25 billion × 60%), providing a general understanding of revenue conditions at each stage for business planning reference.
Q: Looking ahead to 2026, how is the performance of each TPU product line expected to be throughout the year?
A: It is expected that by 2026, the overall sales volume of Google TPU will achieve significant growth, exceeding 3 million units, an increase of over 20% compared to the 2.5 million units in 2025. This growth is mainly attributed to the continuous expansion of AI technology applications and the further release of data center demand. From the performance of each product line, the market landscape will undergo significant changes: on one hand, the TPU V7 series, as a new generation product, will officially launch, while the existing TPU V6 series will gradually replace the V5 series as the market mainstream, and the older TPU V5 series will gradually exit the market due to performance iteration and market demand shifts, although the specific sales composition of each model still needs to be confirmed based on actual production progress and customer orders; on the other hand, the new generation inference chips (such as V6E, V7E) and training chips (such as V6P, V7P) will continue to dominate market demand, becoming the core driving force for sustained overall sales growth, occupying an important position in the AI computing chip market, while also helping Google further consolidate its competitiveness in the AI infrastructure field.
Q: What are the expected shipment volumes for V5E, V5P, V6E, V6P, V7E, and V7P next year?
A: In 2026, the shipment volumes of each model of Google TPU will show a clear trend of new and old iterations. Among them, V5E, due to its performance gradually lagging behind market mainstream demand, will no longer be deployed in new servers, so its shipment volume is expected to be no more than 300,000 units, mainly concentrated in the first and second quarters to meet the upgrade needs of some old servers or supplementary procurement needs of existing customers, after which it will gradually be phased out. For the overall V5 series, the total shipment volume of V5E and V5P in 2026 is expected to be 800,000 units, with most being V5P, about 500,000 units, as V5P’s performance can still meet the training task needs of some medium-sized data centers, while V5E is only about 300,000 units. For the new generation V6 series, the total shipment volume of V6E and V6P in 2026 is expected to reach about 1.6 million units, becoming the main force for the annual shipment volume—V6E has formed stable demand after market promotion in 2025, while V6P, after being launched in the fourth quarter of 2025, will enter a capacity release period in 2026, with a significant increase in shipment volume. As for the higher-end V7 series, the total shipment volume of V7E in 2026 is expected to be close to 500,000 units, as the first product of the V7 series, V7E will focus on high-performance inference scenarios; while V7P, if launched as planned in the fourth quarter, may have an annual shipment volume of up to 100,000 units, but due to factors such as R&D progress, capacity ramp-up, or customer testing cycles, there is also a possibility of being delayed until 2027, at which point its shipment volume for 2026 will be 0.
Q: What is the production cooperation model and market share distribution for the V7 series chips (including V7E and the future V7P)?
A: To optimize the supply chain layout, Google has adopted a diversified cooperation model for the production of V7 series chips (including V7E and the future V7P), with the core goal of testing MediaTek’s delivery capabilities and diversifying supply chain risks to avoid excessive reliance on a single supplier, which could lead to capacity fluctuations or cost pressures. Specifically, Google plans to outsource part of the backend wafer processing work for the V7 series chips to MediaTek, with an expected initial capacity transfer of 20%-30% to MediaTek. It is important to note that this proportion mainly targets chips for Google’s internal use and does not include the chip capacity needed for MediaTek’s own business. In terms of market share distribution, Broadcom, with its chip frontend design, technical accumulation, and the trust established through long-term cooperation with Google, is expected to occupy about 70% of Google’s overall chip procurement share, remaining Google’s primary chip supplier. Additionally, MediaTek has significant advantages in cost control and has a solid foundation in process technology collaboration with TSMC. This “Broadcom as the main supplier, MediaTek as the auxiliary” cooperation model not only helps reduce Google’s chip production costs and improve product market competitiveness but also accumulates experience for further diversification of Google’s supply chain in the future.
Q: What is the pricing strategy for the V7 series chips (including V7E and the future V7P)?
A: The pricing strategy for the V7 series chips (including V7E and the future V7P) is closely related to the product lifecycle, R&D cost allocation, and market positioning, showing a pattern of “high price at launch, gradually decreasing later.” Among them, V7E, as a new generation chip, will be priced at $4,500 to $5,000 at launch, which includes unpaid R&D costs (i.e., NRE costs), which are usually amortized into the price of the first 100,000 chips to quickly recover initial R&D investments; as the initial batch of chips is sold out, production scales up, and R&D costs are amortized, production costs will gradually decrease, so the price of V7E is expected to drop to between $3,000 and $4,000 later, which aligns with the price change patterns of previous models like V6E and V5E, consistent with the industry characteristic of “scale effect cost reduction”. The higher-spec, more technically complex V7P, due to its significantly higher R&D costs and technical content than V7E (such as using more advanced processes, supporting higher computational power, and more complex AI training tasks), is priced close to $10,000, also including NRE costs to share the high R&D costs; however, the specific pricing of V7P may be adjusted based on market competition, customer demand feedback, and capacity conditions at the time of launch, but the overall high-price positioning will not change, mainly targeting high-end data centers and large AI enterprise customers with extreme performance demands.
Q: From a technical process perspective, will the prices of related chips continue to decline in the coming years?
A: From the perspective of technological process development, the prices of related chips (such as Google TPU, Broadcom ASIC, etc.) are expected to continue to decline in the coming years, but the decline will be relatively stable and will not experience drastic drops. The core driving factor for chip price reduction is the continuous improvement of process technology— as chips transition from the current mainstream processes (such as 5nm, 4nm) to more advanced nodes (such as 3nm, 2nm), production efficiency will significantly improve (e.g., more chips can be produced from a single wafer), and raw material and manufacturing costs will gradually decrease as technology matures, all of which will drive down the unit cost of chips, thereby reducing the end price. Based on historical trends in the chip industry and the current pace of technological development, the annual price decline is usually around 5%-10%, mainly reflected in the reduction of wafer processing costs—wafer processing costs are a significant cost item in chip R&D and production. Although advanced process wafer processing costs are high, as technology becomes widespread and production scales up, wafer processing costs will gradually be distributed across more chips, leading to a decrease in unit wafer processing costs. It is important to note that the price decline is predicated on steady technological advancement and timely capacity matching; if there are unexpected situations such as delays in process R&D, capacity shortages, or rising raw material prices, the extent of price decline may shrink, or there may even be slight price increases in the short term, but in the long run, the trend of “technological advancement → cost reduction → price decrease” will not change.
Q: What is the expected revenue scale from Google’s business segments next year?
A: It is expected that the revenue from Google’s business segments in 2026 will be between $15 billion and $16 billion, representing an increase of about 33%-42% compared to $11.25 billion in 2025, showing strong growth momentum. This outlook is based on the current planning of various chip product lines by Google (such as the capacity release of the V6 series and the gradual launch of the V7 series) and corresponding market demand forecasts—AI technology applications will further deepen across various industries in 2026, and the demand for data center construction will remain strong, directly driving an increase in the procurement volume of AI computing chips like TPU; at the same time, the launch of the high-end V7 series chips will also raise the average selling price to some extent, collectively driving revenue growth. However, the specific revenue scale will also be influenced by various factors, such as market competition (e.g., pricing and performance of competitors like NVIDIA and AMD), product price fluctuations (e.g., the extent of price reductions for products like V6E), adjustments in customer orders (e.g., changes in procurement rhythms of large data center customers), and capacity supply conditions (e.g., whether MediaTek can deliver the backend wafer processing capacity for the V7 series on time), so the actual revenue may fluctuate within the range of $15 billion to $16 billion, but the overall trend of steady growth will not change.
Q: Is Google exploring new developments in the design and production of V8 chips? Is there a trend to transfer some design work to MediaTek? What is the specific division of labor and proportion, and what changes may occur in the future?
A: In the development process of the V8 chip, Google is indeed actively exploring supply chain diversification, one important measure being the consideration of transferring some design work to MediaTek, especially for the V8e (the mid-to-low-end version of the V8 series), where Google seems inclined to give MediaTek a larger share of participation to leverage MediaTek’s advantages in cost control and backend manufacturing while further diversifying its reliance on Broadcom. However, from the current progress, the frontend design work of the V8 chip is still mainly handled by Broadcom, primarily because Broadcom has strong technical capabilities in chip frontend design services (such as architecture design, computational power optimization, energy efficiency improvement), which can better meet Google’s requirements for high performance and high stability of the V8 chip, while MediaTek’s experience and technical accumulation in frontend design have not yet fully gained Google’s trust, thus temporarily unable to undertake core frontend design tasks. Based on this, the future division of labor trend may be: frontend design continues to be led by Broadcom to ensure that the core performance of the chip meets standards; while backend design, wafer processing, layout, testing, and packaging will gradually be handed over to MediaTek to fully leverage MediaTek’s cost and manufacturing advantages. However, this division of labor adjustment is not set in stone and ultimately depends on the performance of the V7 series chip wafer processing results in 2026—if MediaTek can complete the backend wafer processing tasks for the V7 series on time and with high quality, Google may further increase MediaTek’s participation ratio in the V8 chip; conversely, if MediaTek’s delivery encounters issues, Google may reduce its participation scope or even revert to relying on Broadcom. Currently, the specific division of labor ratio has not been determined and requires further negotiation and adjustment between Google, Broadcom, and MediaTek based on the actual performance of the V7 series.
Q: What is the revenue growth expectation for Google in 2027? What are the driving factors for this growth?
A: It is expected that by 2027, Google’s overall revenue will maintain a growth rate of 10% to 15%, which is a slowdown compared to the rapid growth in 2025-2026 (about 33%-42%), but still at a relatively high level in the industry. The core driving factor for this growth is the significant increase in chip shipment volumes—as AI technology becomes more widespread globally, various enterprises and institutions will continue to increase their demand for AI computing infrastructure, and Google TPU, as one of the mainstream AI computing chips, is expected to further expand its market share, leading to a significant increase in shipment volumes; at the same time, the V7 series chips will enter a full capacity release period after their launch in 2026, and the V8 series chips may also gradually be introduced in 2027, further driving the growth of shipment volumes and consequently revenue. However, it is important to note that the slowdown in revenue growth is also influenced by two factors: on one hand, to control costs, Google is outsourcing some backend design work of chips to TSMC and MediaTek, which leads to a decrease in the contribution value of each chip (i.e., the revenue generated by each chip), offsetting some of the revenue increase from the growth in shipment volumes; on the other hand, Google’s own R&D capabilities in core module algorithm structures are continuously improving, gradually taking on more internal development tasks, reducing reliance on external cooperation (such as Broadcom’s frontend design services), which, while helping to lower long-term costs, may also impact the revenue growth rate in the short term. Overall, this trend of “shipment volume driving growth, cost control affecting growth rate” reflects the development direction of the design service outsourcing model in the entire chip industry, as Google pursues revenue growth while continuously optimizing its business structure and cost control system to achieve long-term sustainable development.
Q: What are the expected shipment volumes and pricing for Meta’s new training and inference integrated chip (MTIA 2.0) in 2025 and 2026?
A: Meta’s new training and inference integrated chip (MTIA 2.0) is expected to show rapid growth in shipment volumes in 2025 and 2026. Specifically, in 2025, the chip is expected to achieve a shipment target of 300,000 units, with approximately 100,000 units expected to be shipped in September as the starting phase of the year, mainly for customer testing and small-scale deployment; the remaining 200,000 units will be completed in the fourth quarter, with higher shipment volume in the fourth quarter mainly to align with Meta’s own data center deployment plans by the end of the year. By 2026, as product maturity improves and market demand expands, the chip’s shipment volume is expected to increase significantly to 800,000 units, representing an increase of about 167% compared to 2025; from the distribution in the first half and second half of the year, the first half accounts for about 40% (i.e., 320,000 units), and the second half accounts for about 60% (i.e., 480,000 units), with higher shipment volume in the second half, also consistent with the seasonal pattern of concentrated data center deployments. In terms of pricing, the average price of the MTIA 2.0 chip is $9,000, which is higher than Google TPU V5P ($6,000), mainly because it is an integrated training and inference chip, incorporating both training and inference functions, with higher technical complexity; however, as R&D costs are gradually amortized (e.g., NRE costs are fully amortized) and production scales up, the price is expected to drop to around $8,000 by 2026 to enhance the product’s market competitiveness. It is important to note that although the chip’s shipment speed is fast, due to the relatively slow progress of server deployments (servers need to undergo adaptation testing with the chip, which takes a long time), the first quarter of 2026 may need to digest some of the inventory accumulated by the end of 2025 to avoid inventory buildup affecting cash flow and subsequent updates of new products, ensuring the healthy operation of the supply chain.
Q: Will Meta reduce its investment in self-developed ASIC chips and rely on solutions provided by NVIDIA or AMD? What is its long-term goal?
A: Meta has made it clear that it will not change its strategic direction regarding self-developed ASIC chips (such as the MTIA series) and will not reduce its investment in self-developed chips. On the contrary, it plans to continue increasing investment over the next three to five years to achieve comprehensive application and optimization of self-developed chips, making them the core infrastructure for AI computing in its data centers. The core reason for Meta’s insistence on self-developed chips is that they can better meet the specific performance and functional needs of its business—Meta’s business encompasses social networking, short videos, AI recommendations, and other fields, requiring personalized demands for chip computational power, energy efficiency, and adaptability, which general-purpose chips from third-party suppliers like NVIDIA and AMD cannot fully match; at the same time, self-developed chips can help Meta enhance product competitiveness and differentiation, avoiding excessive reliance on external vendors for chip supply, thus reducing risks arising from external supply chain fluctuations (such as capacity shortages and price increases). Additionally, by developing chips independently, Meta can better control product R&D progress, production costs, and quality standards, such as adjusting chip update cycles according to its business iteration pace and optimizing process choices based on cost budgets, which are not achievable through third-party solutions. Therefore, self-developed chips are a crucial part of Meta’s long-term development strategy and a key to building a self-controlled AI infrastructure, which will not be easily changed due to short-term market fluctuations or external competition.
Q: Has Broadcom recently communicated with Meta regarding order or demand adjustments? Have they received any cancellation or demand change notifications?
A: As of now, Broadcom has not received any information from Meta regarding order cancellations or demand adjustments, and the cooperation between the two parties is still proceeding as planned. The last formal communication between the two parties occurred at the end of the second quarter of 2025 (i.e., late June to early July), during which Meta confirmed its chip shipment guidance for the third and fourth quarters of 2025, stating that it would deliver the MTIA 2.0 chips according to the previously agreed quantities and timelines without proposing any changes, indicating that Meta’s chip demand for 2025 remains stable. Furthermore, regarding the cooperation plan for 2026, Broadcom has not yet received any notifications from Meta about adjusting the order scale or delivery time, and both parties are still preparing for the expected shipment of 800,000 MTIA 2.0 chips in 2026 (such as capacity reservation and production planning). However, it is important to note that the cooperation between Broadcom and Meta is relatively short, and a long-term planning mechanism similar to Google’s (e.g., 3-5 years) has not yet been established. The two parties typically update data and demand once a quarter, so future situations still need to be monitored continuously, and there is a possibility that Meta may propose demand changes in subsequent quarters based on its own business adjustments (such as data center construction progress and changes in AI business priorities). According to existing information, Meta’s data center scale deployment plan includes both NVIDIA’s general-purpose chips and self-developed ASIC chips, and it is expected that its demand for ASIC chips will grow by about 30%-40% annually, projecting that by 2027, Meta’s demand for ASIC chips may reach between 1 million and 1.2 million units, with a clear long-term growth trend.
Q: What are the expected chip shipment volumes and pricing for OpenAI from 2025 to 2027?
A: OpenAI’s chip shipment volumes from 2025 to 2027 will show a trend of “starting from low to rapid growth,” with prices gradually decreasing as the scale expands. Specifically, in 2025, OpenAI’s overall chip shipment volume is expected to be no more than 100,000 units, with the low shipment volume mainly due to its chip products still being in the late stages of development and the early stages of market promotion, lacking large-scale production capacity, and also needing time to complete adaptation testing with customers (mainly its own data centers and a few partners), thus limiting shipment volume. By 2026, if chip development proceeds smoothly, production capacity keeps pace, and deployment progresses as expected, OpenAI’s chip shipment volume is expected to achieve exponential growth, reaching around 500,000 units, a 400% increase compared to 2025, mainly driven by the expansion of its AI models (such as the GPT series), leading to a surge in demand for its own chips; at the same time, as the product matures and market recognition increases, external customer orders will gradually increase, further boosting shipment volume. By 2027, based on an annual growth rate of 30%-40%, OpenAI’s chip shipment volume may approach 700,000 to 780,000 units, entering a stable growth period with both production capacity and market demand maturing. In terms of pricing, the chips currently used by OpenAI are primarily for training and are high-performance chips, with a unit price of about $10,000 due to high R&D costs (such as advanced process development and AI algorithm adaptation), which is higher than most mid-to-low-end chips in the industry; it is expected that by 2026, as production scales up (reducing unit costs) and R&D costs are amortized (NRE costs gradually amortized), the price of the chip may drop to between $8,000 and $9,000, with a price reduction of about 10%-20%, making the product more competitive in the market and attracting more external customer orders; by 2027, if shipment volumes continue to grow, prices may further decrease slightly, but the extent of the decline will narrow to balance costs and profits.
Q: What are XAI’s chip shipment plans and pricing situations in the coming years?
A: XAI’s chip business started relatively late, and its shipment plans will gradually advance starting in 2026, with shipment volumes steadily increasing as market demand grows. Specifically, XAI officially started chip design work at the end of 2024, and according to the conventional chip development cycle (design, wafer processing, testing, mass production of about 1.5-2 years), its first chip product is expected to officially ship in the third quarter of 2026; as the first year of shipments, the total shipment volume in 2026 is expected to be about 200,000 units, relatively low, mainly to meet its own AI model training needs and small-scale external customer testing, while also needing time for capacity ramp-up and product optimization. By 2027, as the performance and stability of the chip products are validated in the market, and as XAI’s own AI business expands (such as launching new large models and increasing training scales), market demand for chips will gradually be released, and shipment volumes may increase to around 500,000 units, a 150% increase compared to 2026, entering a rapid growth period with an increase in external customer procurement ratios. In terms of product positioning and pricing, the chip launched by XAI is a small-sized chip mainly used for AI training, designed to control the chip’s size and power consumption while ensuring certain training performance, suitable for small to medium-sized data centers or edge computing scenarios; with this unique product positioning and performance advantages, the chip’s unit price is about $8,000, which is lower than OpenAI’s current $10,000 high-performance training chip and higher than Google TPU V5P ($6,000), placing it at a relatively high level in the market, with certain price competitiveness to meet the needs of customers requiring training performance but not wanting to bear excessive costs.
Q: Is Apple planning to enter the ASIC field? What is the current progress?
A: Apple has not yet finalized whether to enter the ASIC field, and internal discussions and evaluations are still ongoing regarding the “self-development” and “external delivery” models, without forming a clear strategic decision. If Apple ultimately chooses to self-develop ASIC chips, the development cycle is expected to take two to three years—ASIC chip development involves multiple complex stages such as architecture design, process selection, wafer processing testing, and mass production optimization, requiring significant human resources (such as senior chip designers and AI algorithm engineers), material resources (such as R&D equipment and testing platforms), and financial resources (such as wafer processing costs and patent licensing fees), thus having a longer cycle; however, the advantage of self-development is that it can fully match Apple’s customized needs for its business (such as AI functions for iPhone and iPad, model training for data centers) and master core technologies, avoiding reliance on external suppliers. If Apple chooses the external delivery model (i.e., entrusting third-party manufacturers like Broadcom and MediaTek for design and production), the development cycle can be shortened to about one year, allowing for faster product market entry while also reducing its R&D investment and risks; however, the disadvantage of external delivery is that the degree of product customization may be limited, and it requires sharing some demand information with third-party manufacturers, posing certain information security and supply chain dependency risks. Currently, this project is still in the early evaluation stage and has not entered substantive R&D or cooperation negotiation phases, with further news expected in the fourth quarter of 2025—at that time, Apple will comprehensively consider market competition (such as the progress of other tech giants in the ASIC field), its own technical strength (such as the scale and capability of its chip R&D team), strategic planning (such as long-term AI business layout), and cost budget factors to make a final decision on whether to enter the ASIC field and what development model to choose.
Q: What is the expected revenue contribution from the ASIC business to Broadcom? How do the contributions from major customers look?
A: The ASIC business is one of Broadcom’s fastest-growing business segments in recent years, expected to contribute significant revenue with substantial growth potential. Specifically, in 2025, the ASIC business is expected to contribute about $21 billion in revenue, which represents a high proportion of Broadcom’s total annual revenue and has become an important driver of Broadcom’s business growth. In terms of contributions from major customers, Google, as the largest customer of Broadcom’s ASIC business, is expected to contribute about $15 billion, accounting for 71.4% of Broadcom’s total ASIC business revenue in 2025. This high proportion is mainly due to Google’s large-scale procurement of TPU chips (especially the V5 and V6 series), and the long-term stable cooperation relationship between the two parties provides a guarantee for revenue contributions; Meta, as the second-largest customer of Broadcom’s ASIC business, is expected to contribute about $6 billion, accounting for 28.6% of total revenue, mainly from orders for Meta’s self-developed MTIA 2.0 chips, with its contribution expected to increase in the future as Meta’s ASIC demand grows rapidly; OpenAI, due to its relatively low chip shipment volume (expected to be no more than 100,000 units in 2025), will also contribute less to Broadcom’s ASIC business, estimated to be below $1 billion, accounting for less than 5% of total revenue; in addition, there are also small contributions from a few other customers (such as small and medium-sized AI companies and data center operators), which together form the revenue system of Broadcom’s ASIC business, but these customers’ contributions are very low and have little impact on overall revenue. By 2026, as market demand further expands, Broadcom’s ASIC business revenue is expected to grow to $25 billion to $26 billion, an increase of about 19%-24% compared to 2025. In terms of customer contribution changes, Google’s revenue contribution is expected to remain relatively stable, with its chip shipment volume expected to increase by only about 10%, so revenue growth will be relatively steady; while Meta and OpenAI are expected to see significant growth—Meta’s ASIC chip demand is expected to grow by 30%-40% annually, with a substantial increase in shipment volume driving revenue contribution growth for Broadcom; OpenAI is expected to reach a chip shipment volume of 500,000 units in 2026, a 400% increase compared to 2025, which will also significantly boost its revenue contribution to Broadcom, further promoting the development of Broadcom’s ASIC business.
Q: What are the expected shipment volumes for the Jericho series and Tomahawk series chips in 2025?
A: The Jericho series and Tomahawk series are Broadcom’s core product lines in the network chip field, and the expected shipment volumes of each model in 2025 are highly matched with their respective application scenario demands, showing differentiated growth trends. Specifically, the Jericho series chips are mainly positioned for AI data centers, meeting the high bandwidth and low latency data transmission needs of AI data centers. With their high performance and stability, the expected shipment volume in 2025 is about 200,000 units. Although this shipment volume is lower than that of the Tomahawk series, it aligns with the current construction scale of AI data centers and has significant growth potential as AI data centers rapidly develop. The Tomahawk series, as Broadcom’s mainstream network chip series, includes multiple models with significant differences in shipment volumes: among them, Tomahawk 4 is mainly applied to network upgrades of traditional telecom operators (such as upgrading from 100G/200G networks to 400G networks). Due to the strong demand for network upgrades from global telecom operators, the market demand is large, and the expected shipment volume in 2025 is projected to reach 750,000 units, making it the highest shipment volume model in the Tomahawk series; Tomahawk 5 is mainly aimed at mid-to-high-end data centers globally (including the US and China) to support the deployment of 800G networks. As the 800G network technology gradually becomes widespread, its market prospects are broad, with an expected shipment volume of 350,000 units in 2025, second only to Tomahawk 4; Tomahawk 6, as a new product launched in 2025, is mainly positioned for the 1.6T network needs of high-end data centers and is currently only in the early deployment stage, mainly used for market testing and customer feedback collection, so the expected shipment volume in 2025 is only a few thousand units, relatively low; in addition, Tomahawk Ultra (based on Tomahawk 5 design, mainly used to compete with NVIDIA NVLink, meeting the high-speed interconnection needs of AI data centers) is planned to supply a small quantity in 2025, totaling about 100,000 units, mainly to meet the high-performance interconnect chip needs of some high-end customers, with relatively limited shipment volume due to its targeted product nature.
Q: What are the pricing situations for each model of the Jericho series and Tomahawk series chips in 2025?
A: The pricing of each model of the Jericho series and Tomahawk series chips in 2025 is closely related to their product positioning, performance specifications, application scenarios, and market competition, showing clear stratification characteristics. Specifically, the Jericho series chips, as high-performance products for AI data centers, are priced at about $2,500 each. This price positioning mainly considers that this series of chips needs to meet the high bandwidth and low latency transmission needs of AI data centers, with high technical complexity, while also referencing the market prices of similar AI data center network chips, ensuring profitability while maintaining a certain market competitiveness. The Tomahawk 4 chip, due to its wide application in traditional telecom operators’ network upgrades (such as upgrading from 100G/200G to 400G), has a large market demand and relatively fierce competition, with large-scale production and sales effectively controlling unit costs, so its price per unit is relatively affordable, about $1,500, which better meets telecom operators’ cost control needs and promotes large-scale procurement. The Tomahawk 5 chip, compared to Tomahawk 4, has significant performance improvements (such as supporting 800G networks), higher technical complexity, and the mid-to-high-end data center customers it targets are relatively less sensitive to price, so its price per unit is adjusted to between $4,000 and $4,500, reflecting the value increase brought by performance improvements while considering the market’s acceptance of 800G chips, which is the result of Broadcom’s comprehensive considerations. The Tomahawk 6 chip, as a new high-end product launched in 2025, mainly supports the 1.6T network, and its pricing has not yet been fully determined, but based on its high-end positioning, advanced technology, and the price levels of similar 1.6T chips in the market, it is estimated to be around $8,000 per unit. This high price is mainly aimed at high-end data center customers (such as large cloud service providers and AI giants) with extreme network performance demands, making it difficult for ordinary customers to make large-scale purchases in the short term, so the high pricing also aligns with its market positioning.
Q: What are the expected shipment volumes for each model of the Jericho series and Tomahawk series chips in 2026?
A: The expected shipment volumes of each model of the Jericho series and Tomahawk series chips in 2026 will continue the growth trend of 2025, with significant growth rates for some models, mainly due to the sustained release of demand for AI data centers and network upgrades. Specifically, the Jericho series chips are expected to see a shipment volume growth of over 50% in 2026 due to the rapid expansion of AI data center construction, with total shipments exceeding 300,000 units (about 200,000 units in 2025), making this growth rate the fastest among all models, reflecting that AI data centers have become the core growth engine for Broadcom’s network chip business. The Tomahawk 4 chip, mainly applied to network upgrades of traditional telecom operators, achieved a high shipment volume of 750,000 units in 2025, and in 2026, as the global telecom operators’ 400G network upgrades enter the mid-to-late stages, the market demand is relatively stable, so its shipment volume is expected to remain roughly the same as in 2025, maintaining a total scale of 750,000 to 800,000 units without significant growth or decline. The Tomahawk 5 chip, driven by strong demand for 800G switches—more and more data centers will begin deploying 800G networks in 2026—its shipment volume is expected to increase to about 500,000 units (about 350,000 units in 2025), with a growth rate of about 43%, becoming one of the faster-growing models in the Tomahawk series. The Tomahawk 6 chip, as a new product launched in 2025, will enter the deployment promotion stage in 2026, with its shipment volume expected to increase significantly from a few thousand units in 2025 to about 50,000 units, although the absolute shipment volume remains low, the growth multiple is significant, laying the foundation for further expanding market share. Additionally, the Tomahawk Ultra chip is expected to see an increase in shipment volume in 2026 due to the growing demand for high-speed interconnections in AI data centers, although specific data has not yet been released, the overall supply will still remain limited, mainly serving high-end customers.
Q: When was the Tomahawk 6 officially launched in the market?
A: The Tomahawk 6 was officially launched in July 2025, marking a substantial step in Broadcom’s layout in the high-end network chip field (supporting 1.6T networks). However, since the Tomahawk 6 is a new generation product supporting 1.6T networks with high technical complexity, and requires deep adaptation with customers’ switch devices, it did not immediately enter large-scale production and sales after its market launch but is in the early deployment stage. In this stage, Broadcom’s core work includes two aspects: on one hand, assisting customers in testing and adapting the switch operating systems—1.6T network technology has high compatibility and stability requirements for operating systems, requiring Broadcom to work closely with customers (such as switch manufacturers and cloud service providers) to conduct extensive testing to ensure that the Tomahawk 6 chip can seamlessly integrate with customers’ hardware devices and software systems; on the other hand, conducting small-scale customer deliveries and feedback collection—currently, Broadcom is only supplying a small quantity to core customers like Meta and Google for their data center testing environments, collecting feedback on performance, stability, and compatibility through actual usage tests to further optimize the chip and resolve potential technical issues. This early deployment phase typically lasts 3-6 months, and it is expected that by the end of 2025 or early 2026, the Tomahawk 6 will complete early testing and optimization, entering large-scale production and market promotion phases, at which point shipment volumes will significantly increase, becoming an important competitive force for Broadcom in the high-end network chip market.
Q: How to evaluate the distribution ratio of Jericho and Tomahawk 4/5 in each quarter? Is there a reasonable calculation method?
A: Since Broadcom has not directly disclosed the quarterly shipment data for Jericho and Tomahawk 4/5 chips, evaluating their quarterly distribution ratios requires using related business correlation data for indirect estimation, with the most critical reference being the quarterly shipment data of ASIC chips. From industry patterns, data center deployments are usually holistic, meaning that once server deployments are completed, corresponding switches need to be configured (as Jericho and Tomahawk 4/5 are core chips for switches), so the shipment volume of switches typically shows a strong correlation with the shipment volume of ASIC chips (the core computing chips for servers)—when the shipment volume of ASIC chips increases, the shipment volume of switch chips also tends to increase, albeit with a slight time lag (switches are deployed after servers). Although there is currently no detailed historical data to accurately verify this correlation, based on the market trend in 2025, the deployment demand for data centers in the second half of the year is significantly higher than in the first half (for example, the second half shipment proportions of Google TPU and Meta MTIA 2.0 ASIC chips are both 60%), so it can be inferred that, as supporting switch chips, the shipment volumes of Jericho and Tomahawk 4/5 in the second half of 2025 will also be significantly higher than in the first half. Based on this inference, a rough estimate of the annual shipment volume of switch chips can be made at a ratio of 4:6, meaning that the first half accounts for 40% of the annual shipment volume, and the second half accounts for 60%, thus evaluating the distribution ratio of Jericho and Tomahawk 4/5 in each quarter—for example, if Jericho has an annual shipment of 200,000 units, then approximately 80,000 units will be shipped in the first half (200,000 units × 40%), and about 120,000 units in the second half (200,000 units × 60%); further, based on a steady growth trend between quarters, the first half shipment volume can be distributed at a ratio of 1:1.1 between the first and second quarters (e.g., about 38,000 units in the first quarter and about 42,000 units in the second quarter), while the second half can be distributed at a ratio of 1:1.5 between the third and fourth quarters (e.g., about 48,000 units in the third quarter and about 72,000 units in the fourth quarter). It is important to note that this calculation method is a rough estimate, and the actual quarterly distribution ratios may be adjusted due to customer order rhythms, capacity supply conditions, or sudden demand changes, but overall it can still provide reasonable reference for Broadcom’s production planning, inventory management, and customer order responses.
Q: What is the development background, technical characteristics, and competitive situation of the UAlink standard compared to NVLink?
A: The UAlink standard was born against the backdrop of the growing demand for high-speed interconnections in AI data centers and the bottlenecks of existing Ethernet technology, closely related to the market monopoly of NVLink and the technical limitations of Ethernet. Specifically, as the scale of AI models expands (such as hundreds of billions or trillions of parameters), the demand for data transmission between multiple chips within data centers surges, posing high requirements for bandwidth and latency; NVIDIA’s NVLink, as the current mainstream high-speed interconnection technology, monopolizes the high-end AI data center interconnection market due to its advantages of high bandwidth and low latency, which exposes other chip manufacturers and data center customers to supply chain dependency risks; at the same time, traditional Ethernet, due to its packet transmission form, has higher latency (usually in the hundreds of nanoseconds), failing to meet the low-latency requirements of AI computing. Therefore, more than a dozen companies, including Broadcom, jointly initiated the UAlink standard in 2023, aiming to benchmark NVIDIA’s NVLink, break its monopoly, and address Ethernet’s shortcomings in latency and bandwidth, with participating companies including AMD, Cisco, and China’s Ruijie, forming a diversified ecological alliance.
In terms of technical characteristics, the core goal of the UAlink standard is to achieve performance comparable to NVLink while maintaining the compatibility and flexibility of Ethernet. From the information released so far, NVLink has a bandwidth about four times higher than traditional PCIe interfaces, with latency as low as 100 nanoseconds, meeting the needs for multi-chip collaborative training; while the UAlink 1.0 version was released in 2024, its corresponding commercially available chips are expected to be launched by 2027, mainly due to the high difficulty of developing high-speed interconnection chips, which need to address multiple technical challenges such as signal integrity and power consumption control. To fill the market demand gap before 2027, Broadcom has launched transitional solutions: for example, products based on the Tomahawk Archer 5.0 design can achieve latency below 200 nanoseconds, although higher than NVLink, but significantly lower than traditional Ethernet; while the new generation 2.0 product based on Tomahawk 6, planned for release in 2026, is expected to reduce latency to around 100 nanoseconds, close to the performance of NVLink 7.0. These transitional products can provide customers with alternative choices before the UAlink ecosystem matures, alleviating dependence on NVLink.
In terms of competition with NVLink, UAlink is still in a catch-up phase and is unlikely to completely replace NVLink in the short term, but it is expected to form a competitive landscape in the long run. The advantage of NVLink lies in its mature ecosystem—NVIDIA has built a complete ecosystem from chips, interconnections to software, making customer migration costs high; while UAlink’s advantages lie in its openness and compatibility, being promoted by multiple manufacturers without a single vendor monopoly, and can be compatible with the existing Ethernet ecosystem, reducing customers’ deployment costs. However, UAlink faces two major challenges: first, the commercial chip launch time is relatively late (2027), during which NVLink may further upgrade and expand its performance advantages; second, ecosystem construction takes time, requiring more chip manufacturers, equipment manufacturers, and software vendors to participate to form an ecosystem that can compete with NVLink. Overall, the launch of UAlink provides new choices for the market and helps break NVLink’s monopoly, but the future competition with NVLink will be long-term, depending on various factors such as technical performance, ecosystem maturity, and customer acceptance.
Q: How does AMD plan to compete with NVIDIA through the MI450 chip and its related architecture? What interconnection technology is currently used in the scale-up architecture?
A: AMD plans to compete with NVIDIA in the AI chip market through performance optimization, cost control, and architectural innovation of the MI450 chip, with the core strategy being to create products with “high cost performance + differentiated features” to attract cost-sensitive and customized demand customers. Specifically, the MI450 is a general-purpose AI chip launched by AMD, aiming to compete with NVIDIA’s mainstream products like A100 and H100 in AI training and inference scenarios; in terms of performance, AMD optimizes the process technology (such as using advanced 5nm processes), enhances computational power density (such as FP16 computational power, TPU computational power), and improves energy efficiency (reducing power consumption per TOPS), making the MI450’s performance in certain AI tasks (such as computer vision and natural language processing) comparable to NVIDIA’s similar products; in terms of cost, AMD sets the price of MI450 to be 10%-20% lower than NVIDIA’s similar products, attracting medium-sized data centers and AI startups; in terms of differentiated features, the MI450 supports more open-source AI frameworks (such as deep optimizations for TensorFlow and PyTorch) and provides more flexible customization interfaces, allowing customers to adjust chip functions according to their business needs, which is highly attractive to customers requiring personalized AI solutions. Additionally, AMD is building an ecosystem around the MI450, such as collaborating with server manufacturers to launch hardware devices compatible with MI450 and working with software vendors to optimize AI applications, further enhancing product competitiveness and gradually expanding its market share in the AI chip market.
In the scale-up architecture (i.e., horizontal expansion architecture, enhancing overall computational power through multi-chip collaboration), AMD currently mainly uses PCIe (Peripheral Component Interconnect Express) as the interconnection technology, specifically including PCIe 5.0 and PCIe 6.0 versions. Among them, PCIe 5.0 supports 16 lanes with a bandwidth of up to 64GB/s; PCIe 6.0 also supports 16 lanes, with bandwidth further increased to 128GB/s, meeting the data transmission needs between multiple chips in medium to large-scale AI computing. As a mature interconnection technology, PCIe has advantages of low latency (compared to Ethernet), strong compatibility (supporting various hardware devices), and lower costs, suitable for AMD’s current scale-up architecture needs. However, PCIe also has certain limitations: its transmission distance is limited, and when communicating between chips (or cards), if the distance exceeds a certain range (e.g., more than 1 meter), it requires the use of retimers (signal repeaters) to extend the transmission distance, which adds certain costs and complexity; in addition, compared to NVIDIA’s NVLink, PCIe still has bandwidth gaps (NVLink 7.0 can reach hundreds of GB/s), which may affect the efficiency of multi-chip collaboration in ultra-large-scale AI training scenarios. Therefore, AMD is also actively developing more advanced interconnection technologies and may launch high-speed interconnection technologies based on the UAlink standard or self-developed technologies in the future to further enhance the performance of the scale-up architecture and better compete with NVIDIA.
Q: How has Broadcom’s acquisition of VMware impacted the revenue contribution of this business segment to the company? What core functionalities does VMware provide?
A: After Broadcom’s acquisition of VMware, the VMware business segment has become one of Broadcom’s important sources of revenue, and its revenue contribution ratio continues to rise, playing a key supporting role in Broadcom’s overall revenue growth. Specifically, at the time of Broadcom’s acquisition, VMware’s annual revenue was about $10 billion to $15 billion, demonstrating strong market profitability and business scale; with Broadcom’s integration and promotion of VMware’s business, VMware’s revenue has maintained stable growth, and by 2026 (the year after the acquisition), it is expected that VMware will account for about 40% of Broadcom’s overall revenue, indicating that VMware has become Broadcom’s second-largest revenue source after the chip business, significantly enhancing Broadcom’s revenue scale and risk resistance—when the chip business is affected by market fluctuations, VMware’s stable revenue can buffer risks and ensure the overall performance of Broadcom remains stable.
VMware’s core functionality is to provide virtualization solutions for data centers, which are the foundation for the efficient operation of modern data centers, mainly including the following aspects: first, multi-system compatibility support, VMware’s virtualization technology can run multiple different operating systems on the same physical server, such as Linux, Unix, and Windows, breaking down compatibility barriers between operating systems, allowing servers to simultaneously host various applications and algorithms, significantly improving server resource utilization; second, resource scheduling and management, through virtualization technology, VMware can abstract the CPU, memory, storage, and other hardware resources of physical servers into virtual resources, dynamically allocating resources based on application needs, avoiding resource waste, while supporting load balancing to ensure the stability and efficiency of data center operations; third, disaster recovery and security, VMware provides comprehensive disaster recovery solutions, such as virtual machine backups and rapid recovery functions, enabling quick restoration of data and services in the event of system failures, reducing business interruption losses; at the same time, its virtualization isolation technology can isolate the operating environments of different applications, reducing the impact of a single application’s failure on others, enhancing the security of data centers. However, it is important to note that some users have reported that VMware’s product pricing is relatively high, which may lead some cost-sensitive customers (such as small and medium-sized enterprises) to turn to lower-cost virtualization solutions provided by vendors like Alibaba Cloud and AWS. Therefore, Broadcom needs to pay attention to this issue in its subsequent operations, optimizing product pricing strategies to balance profits and market share, ensuring the long-term stable development of VMware’s business.
Q: What changes have occurred in VMware’s user strategy after Broadcom’s acquisition? What specific aspects are reflected?
A: After Broadcom’s acquisition of VMware, significant adjustments were made to its user strategy to enhance VMware’s profitability and operational efficiency, with the core direction being to “abandon low-value individual users and focus on high-value enterprise customers,” with specific changes reflected in user group segmentation, service models, and pricing strategies.
In terms of user group segmentation, Broadcom changed VMware’s previous strategy of “covering all user groups, both individual and enterprise,” and clearly stratified users based on value. Originally, VMware’s users were divided into two categories: one category was individual users, including schools, small institutions, and individual developers, who mostly used VMware’s free or low-cost versions (such as VMware Workstation Player). Although this user group is large, it has low profitability and requires significant customer service resources for maintenance; the other category was enterprise customers, including large enterprises, cloud service providers, and government agencies, who purchase VMware’s high-end paid versions (such as VMware vSphere Enterprise Plus), have strong purchasing power, pay higher fees, and have high requirements for service stability and professionalism. Broadcom believes that the investment return ratio for individual users is too low, so it has basically abandoned this part of the market, no longer updating features for individual user versions and gradually reducing customer service support for individual users, while concentrating resources on enterprise customers.
In terms of service models, Broadcom shifted VMware’s service model from “generalized service” to “customized enterprise-level service.” Previously, VMware provided standardized service processes for all users, which could not meet the personalized needs of enterprise customers; after the acquisition, Broadcom launched customized services for enterprise customers, such as dedicated account managers, customized solution design, 7×24 technical support, etc., while strengthening long-term cooperation with enterprise customers, providing forward-looking technical support and product upgrade suggestions based on customers’ business development plans (such as data center expansion and cloud transformation), increasing enterprise customers’ stickiness. Additionally, Broadcom has promoted collaboration between VMware and its chip business, providing integrated solutions of “chips + virtualization software” for enterprise customers, such as optimizing VMware’s virtualization software for Broadcom ASIC chips to enhance overall operational efficiency, further increasing attractiveness to enterprise customers.
In terms of pricing strategies, Broadcom adjusted VMware’s pricing system for enterprise customers from “fixed pricing” to “flexible pricing based on value.” Previously, VMware’s pricing was mainly based on product versions and functional modules, with relatively fixed prices; after the acquisition, Broadcom developed differentiated pricing plans based on enterprise customers’ scale (such as the number of servers and users), usage scenarios (such as AI data centers and traditional enterprise IT), and service needs (such as customized development and disaster recovery services), appropriately raising prices for high-demand, high-value customers, while providing discounts for long-term cooperation or large-scale procurement customers, ensuring profit margins while increasing large customers’ willingness to purchase.
Overall, this series of user strategy adjustments by Broadcom aims to enhance VMware’s profitability and market competitiveness by focusing on high-value enterprise customers while reducing resource consumption from low-value businesses, aligning with Broadcom’s overall “high profit, high growth” business strategy.
Q: Has Broadcom recently shown outstanding performance in traditional networking fields (such as wireless, storage, broadband, industrial networking, etc.)?
A: Broadcom’s performance in traditional networking fields (including wireless, storage, broadband, industrial networking, etc.) shows a “differentiated characteristic”—sub-segments related to data centers (such as optical chips and storage devices) have performed relatively well, becoming growth highlights in traditional networking fields; while consumer or more mature sub-segments (such as Bluetooth and Wi-Fi) have shown moderate growth, with overall performance not experiencing a comprehensive explosion.
Specifically, the sub-segments that have performed well are mainly optical chips and storage devices: on one hand, with the rapid expansion of global data centers, the demand for high-speed optical chips has surged—optical chips are core components for high-speed data transmission within and between data centers, used for signal processing of high-speed optical modules such as 100G, 400G, and 800G. Broadcom, leveraging its technical accumulation in optical chips (such as high bandwidth and low power consumption designs), has secured numerous orders from data center customers (such as Google, Meta, and AWS), with revenue and shipment volumes in the optical chip business achieving double-digit growth; on the other hand, the expansion of data centers has also driven the demand for storage devices—data centers need to store massive amounts of AI training data and user data, leading to a significant increase in demand for high-performance storage devices (such as SSD controllers and storage array chips), with Broadcom’s storage device chips occupying a high market share due to their high reliability and high read/write speeds, and related business revenues maintaining stable growth, becoming an important growth engine in traditional networking fields.
In contrast, the performance of consumer technology departments such as Bluetooth and Wi-Fi has been relatively flat: these departments mainly serve the consumer electronics market (such as smartphones, tablets, and smart home devices), and the market has now entered a mature phase, with demand growth mainly relying on the replacement cycle of consumer electronics rather than driven by technological innovation, so growth rates are typically around 10%, sometimes even single-digit growth, far below the growth rates of data center-related fields like optical chips and storage devices. Additionally, these consumer technology departments face two major challenges: first, customer concentration is relatively high; for example, in the Wi-Fi business, the largest customer is Apple’s product line, and Apple’s procurement volume directly impacts Broadcom’s Wi-Fi business revenue. If Apple adjusts its supply chain (such as introducing other suppliers), Broadcom’s Wi-Fi business will face significant risks; second, the market competition is fierce, with many manufacturers (such as MediaTek and Qualcomm) competing with Broadcom in the consumer wireless chip field, using low-price strategies to capture market share, which squeezes Broadcom’s profit margins in these areas.
Overall, Broadcom’s outstanding performance in traditional networking fields is mainly concentrated in sub-segments related to AI data centers, which inject new vitality into traditional networking businesses; while consumer sub-segments are constrained by market maturity and competition, showing sluggish growth. In the future, Broadcom needs to further increase R&D investment in data center-related technologies in traditional networking fields while enhancing the competitiveness of consumer businesses through technological innovation and cost control to achieve balanced development in traditional networking fields.
Q: How do the growth curves of non-AI related networking businesses compare to AI related businesses?
A: There is a significant difference in the growth curves between non-AI related networking businesses and AI related businesses, with AI related businesses showing a “high-speed growth” trend, while non-AI related networking businesses exhibit a “slow growth” trend, with a clear gap in growth rates, reflecting the current market’s high emphasis on AI technology and resource allocation.
Specifically, AI related businesses (mainly including chips, interconnections, storage, etc. for AI data centers, such as Broadcom’s ASIC chips, Jericho series network chips, optical chips, Google’s TPU, etc.) are experiencing extremely rapid growth, with the industry average growth rate currently around 30% to 40%, and some leading companies (such as Broadcom and NVIDIA) seeing growth rates in their AI related businesses exceeding 50%. The core driving factor for this high-speed growth is the rapid proliferation of AI technology globally—from internet giants (such as Google and Meta) to traditional enterprises (such as those in finance, manufacturing, and healthcare), all are increasing their investments in AI infrastructure to support the training, inference, and application deployment of AI models, directly driving a surge in demand for AI chips, high-speed interconnection devices, and high-performance storage; at the same time, continuous innovations in AI technology (such as the expansion of large model scales and the development of multimodal AI) are also driving the upgrade of existing AI infrastructure, further accelerating the growth of AI related businesses, making them the core growth engine of the entire technology industry.
In contrast, non-AI related networking businesses (mainly including traditional telecom and enterprise network upgrades, consumer wireless businesses, etc., such as Broadcom’s Tomahawk 4 chips, Bluetooth chips, Wi-Fi chips, and traditional telecom operators’ 4G/5G network maintenance, etc.) are expected to have relatively slow growth, with an average industry growth rate of only about 10% to 15%, and some mature areas (such as traditional telecom network upgrades) experiencing growth rates even below 10%. This slow growth is mainly due to two reasons: on one hand, the market for non-AI related networking businesses has entered a mature phase, with demand growth mainly relying on the replacement of existing equipment and slight expansions in the incremental market (such as telecom network construction in emerging markets), rather than explosive demand driven by technological innovation, thus limiting growth potential; on the other hand, non-AI related networking businesses face intense market competition, with numerous manufacturers (such as MediaTek, Qualcomm, and Huawei) laying out in this field, competing fiercely through price wars and homogeneous competition to capture market share, making it difficult for companies to achieve high-speed growth through price increases or expanded sales, while also limiting profit margins, further constraining the speed of business expansion.
Overall, AI related businesses have greater development potential and market space, serving as the core driving force for growth in the technology industry in the coming years; while non-AI related networking businesses will maintain steady growth, providing a stable cash flow as the “foundation” for enterprises. For companies like Broadcom that are simultaneously laying out both business areas, it is necessary to increase business layout and R&D investment in the AI field to align with market development trends while maintaining the stability of non-AI related networking businesses, achieving synergistic development between “high-growth businesses” and “stable businesses.”
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