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Introduction to DDS:
DDS, like DSP (Digital Signal Processing), is a key digital technology. DDS stands for Direct Digital Synthesizer. Compared with traditional frequency synthesizers, DDS has advantages such as low cost, low power consumption, high resolution, and fast conversion time, widely used in telecommunications and electronic instruments, making it a key technology for achieving full digitalization of devices. The functions of DDS chips mainly include frequency control registers, high-speed phase accumulators, and sine calculators. The frequency control register can load and store user-input frequency control codes in serial or parallel mode; the phase accumulator performs phase accumulation according to the frequency control code in each clock cycle to obtain a phase value; the sine calculator calculates the digitized sine wave amplitude based on that phase value (the chip generally obtains it through a lookup table). The output of the DDS chip is generally a digitized sine wave, so it needs to go through a high-speed D/A converter and a low-pass filter to obtain a usable analog frequency signal. For those who want to know more about DDS, you can search directly on Baidu. Below, we will mainly introduce the design of the FPGA program, configuration, and debugging of the DDS IP.
Writing the Verilog program for dds_wave
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:01:33 07/17/2018
// Design Name:
// Module Name: dds_wave
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 – File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dds_wave(clk, key1,data,da_clk
);
input clk, key1;
output [7:0] data;
output da_clk;
reg [15:0] key1_cout;
reg [7:0] data_o;
reg dds_we;
reg [28:0] dds_data;
reg [3:0] dds_freq = 0;
reg dds_we_req;
wire [7:0] sine;
assign sine_reg = sine[6:0];
assign da_clk = clk;
assign data = data_o;
// Convert signed number to unsigned output to DA
always @(posedge clk)
begin
if(sine[7] == 1’b1)
data_o <= sine – 128;
else
data_o <= sine + 128;
end
// Control DDS output frequency
always @(negedge clk)
begin
dds_we <= dds_we_req;
case(dds_freq)
4’d0:
dds_data <= 29’d107;//10Hz:(dds_data*2^29/50*1000000)
4’d1:
dds_data <= 29’d1074;//100Hz:(dds_data*2^29/50*1000000)
4’d2:
dds_data <= 29’d10737;//1kHz:(dds_data*2^29/50*1000000)
4’d3:
dds_data <= 29’d53687;//5kHz:(dds_data*2^29/50*1000000)
4’d4:
dds_data <= 29’d107374;//10kHz:(dds_data*2^29/50*1000000)
4’d5:
dds_data <= 29’d536871;//50kHz:(dds_data*2^29/50*1000000)
4’d6:
dds_data <= 29’d1073742;//100Hz:(dds_data*2^29/50*1000000)
4’d7:
dds_data <= 29’d5368709;//500Hz:(dds_data*2^29/50*1000000)
4’d8:
dds_data <= 29’d10737418;//1mHz:(dds_data*2^29/50*1000000)
4’d9:
dds_data <= 29’d21474836;//2mHz:(dds_data*2^29/50*1000000)
4’d10:
dds_data <= 29’d32212255;//3mHz:(dds_data*2^29/50*1000000)
4’d11:
dds_data <= 29’d42949672;//4mHz:(dds_data*2^29/50*1000000)
4’d12:
dds_data <= 29’d53687091;//5mHz:(dds_data*2^29/50*1000000)
4’d13:
dds_data <= 29’d64424509;//6mHz:(dds_data*2^29/50*1000000)
4’d14:
dds_data <= 29’d75161928;//7mHz:(dds_data*2^29/50*1000000)
4’d15:
dds_data <= 29’d85899346;//8mHz:(dds_data*2^29/50*1000000)
default:
dds_data <= 29’d107;// 1kHz:(dds_data*2^29/50*1000000)
endcase
end
// Button handler to change DDS output frequency
always @(posedge clk)
begin
if(key1 == 1’b0)
key1_cout <= 0;
else if((key1 == 1’b1) & (key1_cout <= 16’hc350))
key1_cout <= key1_cout + 1’b1;
if(key1_cout == 16’hc349)
begin
dds_freq <=dds_freq + 1’b1;
dds_we_req <= 1’b1;
end
else begin
dds_freq <=dds_freq;
dds_we_req <= 1’b0;
end
end
// DDS IP generates sin/cos waveforms
sin_cos sin_cos_inst(
.clk(clk),
.we(dds_we),
.data(dds_data),
.cosine(cosine),
.sine(sine),
.phase_out()
);
endmodule
The program detects the button KEY1 on the development board; each time the button KEY1 is pressed, the value of the register dds_freq increases by 1, and the program writes a data value to the DDS IP to change the phase increment, thereby changing the output waveform frequency. The program sets 16 different phase increments, allowing the DDS to generate 16 different frequency sine waves. In this experiment’s DDS IP configuration, the phase increment data width is 29 bits, so the minimum frequency output is 50Mhz/2^29, approximately 0.093Hz. To output a 1Khz waveform from the DDS, a phase increment value of 10737 needs to be written. The calculation formula for phase increment value and frequency is as follows:
Phase Increment Value=( fhz * 2^29 )/( 50 * 1000000)
Simulation diagram as follows:
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