Learning STM32 development inevitably involves the step of debugging. This article will help you understand the knowledge related to debugging.
This article takes STM32F1 and Cortex-M3 as examples; the principles are the same or similar for other series of chips or cores.
1Overview
In STM32, there are many debugging components. Using them allows for various debugging functions, including breakpoints, data watchpoints, flash address remapping, and various tracing.
STM32F1 uses the Cortex-M3 core, which contains a hardware debugging module that supports complex debugging operations.
The hardware debugging module allows the core to stop when fetching instructions (instruction breakpoints) or accessing data (data breakpoints). When the core stops, both the internal state of the core and the external state of the system can be queried. After the query is completed, the core and peripherals can be restored, and the program will continue execution.
When the STM32F10x microcontroller is connected to the debugger and debugging begins, the debugger will perform debugging operations using the core’s hardware debugging module.
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Debugging Block Diagram
The debugging block diagram of STM32F1 and Cortex-M3:
Tip: The hardware debugging module contained in the Cortex-M3 core is a subset of the ARM CoreSight development toolset.
The ARM Cortex-M3 core provides integrated on-chip debugging capabilities. It consists of the following components:
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SWJ-DP: Serial/JTAG Debug Port
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AHP-AP: AHB Access Port
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ITM: Instrumentation Trace Macrocell
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FPB: Flash Patch and Breakpoint Unit
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DWT: Data Watchpoint and Trace
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TPUI: Trace Port Interface Unit (only supported on larger package chips)
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ETM: Embedded Trace Macrocell (supported on larger packages with pins for this function), dedicated to debugging features of STM32F1
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Flexible debugging pin assignment
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MCU Debug Box (supports low power modes, controls peripheral clocks, etc.)
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Debugging Interfaces
STM32 supports two debugging interfaces:
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Serial Interface
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JTAG Debug Interface
The 5 general I/O pins of STM32 can be used as SWJ-DP (Serial/JTAG Debug) interface pins:
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SWJ Debug Port (Serial Wire and JTAG)
The STM32 core integrates a Serial/JTAG debug interface (SWJ-DP). This is the standard ARM CoreSight debug interface, which includes the JTAG-DP interface (5 pins) and the SW-DP interface (2 pins).
1. JTAG Debug Interface (JTAG-DP) provides a 5-pin standard JTAG interface for the AHP-AP module.
2. Serial Debug Interface (SW-DP) provides a 2-pin (clock + data) interface for the AHP-AP module.
In the SWJ-DP interface, the 2 pins of the SW-DP interface and some of the 5 pins of the JTAG interface are multiplexed.
SWJ Debug Port:
The above figure shows that the asynchronous trace output pin (TRACESWO) and TDO are multiplexed. Therefore, the asynchronous trace function can only be implemented on the SWDP debug interface and cannot be implemented on the JTAG-DP debug interface.
Mechanism for Switching Between JTAG-DP and SW-DP
The JTAG debug interface is the default debugging interface. If the debugger wants to switch to SW-DP, it must output a specified JTAG sequence on TMS/TCK (mapped to SWDIO and SWCLK), which disables JTAG-DP and activates SW-DP. This method can activate the SW-DP interface using only the SWCLK and SWDIO pins.
The specified sequence is:
1. Output TMS (SWDIO) = 1 signal for more than 50 TCK cycles
2. Output 16 TMS (SWDIO) signals 0111100111100111 (MSB)
3. Output TMS (SWDIO) = 1 signal for more than 50 TCK cycles
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Internal Pull-Up and Pull-Down on JTAG Pins
It is necessary to ensure that the JTAG input pins are not floating, as they are directly connected to D flip-flops that control the debug mode. Special attention must be paid to the SWCLK/TCK pins, as they are directly connected to the clock terminals of some D flip-flops.
To avoid any uncontrolled I/O levels, STM32 embeds internal pull-ups and pull-downs on the JTAG input pins.
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JINTRST: Internal pull-up
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JTDI: Internal pull-up
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JTMS/SWDIO: Internal pull-up
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TCK/SWCLK: Internal pull-down
Once the JTAG I/O is released by user code, the GPIO controller regains control. The state of these I/O pins will revert to their state at reset.
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JNTRST: Input with pull-up
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JTDI: Input with pull-up
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JTMS/SWDIO: Input with pull-up
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JICK/SWCLK: Input with pull-down
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JTDO: Floating input
Software can use these I/O pins as ordinary I/O pins.
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Utilizing Serial Interface and Releasing Unused Debug Pins as Ordinary I/O Pins
To utilize the serial debug interface to free some ordinary I/O pins, user software must set SWJ_CFG=010 after reset, thereby releasing PA15, PB3, and PB4 for use as ordinary I/O pins.
During debugging, the debugger performs the following actions:
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At system reset, all SWJ pins are assigned as dedicated pins (JTAG-DP + SW-DP).
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In the system reset state, the debugger sends the specified JTAG sequence to switch from JTAG-DP to SW-DP.
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Still in the system reset state, the debugger sets breakpoints at the reset address
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Releases the reset signal, and the core stops at the reset address.
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From here, all debugging communication will use the SW-DP interface, and other JTAG pins can be repurposed by user code as ordinary I/O pins.
Tip: This is where everyone needs to configure the relevant pins.
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References
1.Cortex-M3 (r1p1 version) Technical Reference Manual (TRM)
2.ARM Debug Interface V5
3.ARM CoreSight Development Toolset (r1p0 version) Technical Reference Manual
Note: This article refers to the “STM32F1 Reference Manual” and the “CM3 Technical Manual”.
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