Energy Saving Methods in Embedded Systems

Dynamic power consumption is proportional to clock speed and is a significant component of computer system power consumption. Reducing CPU load is one method to decrease power consumption, while another method is to lower the CPU clock speed in idle mode.

In most computing systems, the CPU is the primary energy consumer. The dynamic power consumed by the CPU depends on the clock frequency and the time spent in idle mode. Modern CPUs have one or more instructions that can be used during idle time; in ARM architecture processors, the instructions are WFI (Wait For Interrupt) or WFE (Wait For Event). These instructions gate the clock to a part of the CPU, eliminating dynamic power consumption when the CPU is idle.

Typical code implementation:

OS_Idle(void) {  for (;;) {        __wfi();      }}

It makes sense to reduce the time the CPU spends executing code to maximize idle time, which can be achieved through efficient programming (smart algorithms), good compilers, and efficient runtime libraries.

Another key point in embedded system implementation is to avoid waiting for hardware (as shown in the example below):

// Wait until data is readywhile (NAND_FLASH_BUSY);  

Let the ready signal trigger an interrupt, or execute periodic checks or delays in a loop (such as OS_TASK_Delay_us(30)). SEGGER’s embOS-Ultra allows delays to be set in microseconds, which is perfect for the short delays typically required by hardware.

In most cases, interrupts are the best method, but they require hardware capable of generating the corresponding interrupts, are not universal, and require more work from the programmer.

There is still dynamic power consumption in idle mode! This is because certain components (such as the interrupt controller) always have a clock. Therefore, even when the CPU is in idle mode, its dynamic power consumption is still proportional to the clock speed, which means that lowering the clock speed in idle mode is a power-saving method.

The power consumption in idle mode is lower than during program execution, but it is still quite high. We found that in the Xilinx Zynq chip used in J-Link and Flasher, the power consumption when idle is about 50% of that during program execution. At a main frequency of 600MHz, the CPU consumes about 45mW of dynamic power; reducing the speed to 200 MHz measures approximately a savings of 30 mW. This means that if we modify OS_Idle() accordingly, we can save about 30mW!

OS_Idle(void) {  for (;;) {                      //  Implemented in a hardware layer, usually only a single write to an sfr to change the clock dividerHW_CPU_SetIdleSpeed();        __wfi();                    }}

In a well-designed system, the CPU is idle most of the time. The downside is that after each interrupt occurs, the CPU needs to switch back to a higher speed (or at least those CPUs that must respond quickly). The CPU’s response to interrupts may be slightly slower, but if the CPU runs at 1/16 of its original speed, it should not significantly affect response time. Alternatively, just reduce it to 1/2, which can still save 50% of dynamic idle consumption.

However, ARM combines the system timer in the Cortex CPU with the CPU frequency, lowering the CPU frequency also reduces the system timer’s frequency. If the system timer is used for timing, this will cause problems.

The solution is to dynamically reprogram the system timer when changing the CPU speed or to use timers with different time bases.

There are other sources of power consumption (leakage) in embedded systems, and many things can be done to reduce the power consumption of embedded systems. But lowering the CPU speed in idle mode has an astonishing effect!