When the LCD screen displays abnormally, in the past, we would deduce the parameters through the phenomenon, which was time-consuming and labor-intensive. With the long-storage oscilloscope, debugging the LCD controller is no longer a headache. The following text shares the application of the ZDS4054Plus in LCD testing through practical cases.

1. Working Principle of LCD Controller and Driver

To display text or images on the LCD, the LCD controller outputs RGB data to the LCD driver, which then places the data into a buffer and refreshes the LCD screen at a speed of 60 frames per second. (Due to the characteristics of liquid crystal molecules: when they are fixed at a constant voltage for a long time, it can damage the liquid crystal molecules, so the LCD screen must be refreshed continuously at a certain frequency (usually 60Hz). Although the frame rate of video playback is only 23-30 frames per second, the refresh rate of the TFT-LCD display reaches 60Hz. The LCD controller controls the video frame rate; the LCD driver controls the display refresh rate.)

The LCD controller controls each pixel through different combinations of row and column signals. This row scanning (HYNC) signal has a very short period (up to 40kHz-100kHz), allowing the screen to display stable images.

The signal timing and working principle of the LCD controller are as follows:

• VSYNC: Frame synchronization signal, indicating the start of scanning one frame, which is one picture displayed by the LCD;

• HSYNC: Line synchronization signal, indicating the start of scanning one line;

• VCLK: Pixel clock signal, each pulse fills one pixel;

• VDEN: Data enable signal, when high, the filled data is valid;

• VD[23:0]: LCD pixel data output port.

• LEND: Line end signal;

Taking a 1024X768 pixel LCD screen as an example, to completely display an image on the screen, the signal must contain 1 VSYNC cycle, 768 valid HSYNC cycles, and each VDEN high level must contain 1024 pixel clock signals. Problems with the display can be diagnosed through the frequency, duty cycle, and delay of the frame synchronization signal, line synchronization signal, the number of HSYNC cycles contained in each VSYNC cycle, and the number of VSCLK cycles contained in the VDEN cycle.

2. Using the ZDS4054Plus Oscilloscope to Solve LCD Display Anomalies

1. Image Overlapping and Repetition

Phenomenon: A large area of the image on the LCD display is misaligned, overlapped, or repeated;

Cause: This situation is generally not caused by delays in line synchronization or frame synchronization signals, so these influences can be basically ruled out. Check for differences in timing or clock frequency.

Solution: When encountering this situation, the first thing to do is to carefully calculate the DMA transmission parameters and accurately adapt the line and field signals.

As shown in the oscilloscope screenshot, the corresponding signals for each channel are VCLK, VSYNC, VHSYNC, and VDEN signals. The analysis steps are as follows:

1) Since the time for a complete frame signal usually exceeds 30ms, the oscilloscope needs to be set to 10ms/div time base, while the frequency of the VCLK signal can reach 48-96MHz, and the sampling rate must be maintained at least 500Ms/s to analyze the timing. At this time, ordinary oscilloscopes cannot capture the waveform completely.

2) The ZDS4054Plus can still maintain a sampling rate of 1Gs/s at a time base of 10ms/div, perfectly restoring the waveform. Combined with the hardware frequency meter equipped with each channel, it can analyze whether there are any anomalies in the frequency of each signal;

2. Image Misalignment

Phenomenon: The LCD display is displaced in the horizontal direction, or there are colored, white, or black stripes of several pixels at the top or bottom.

Cause: Generally speaking, this situation is related to frame synchronization and line synchronization signals. If it is a constant anomaly, it may be due to incorrect initialization parameter settings; if it is an intermittent anomaly, it may be due to interference received by frame synchronization and line synchronization signals during operation.

Solution: Check the width, front and back delays, and polarity matching of the line synchronization and field synchronization signals of the LCD controller.

As shown in the oscilloscope screenshot, the corresponding signals for each channel are VCLK, VSYNC, VHSYNC, and VDEN signals. The analysis steps are as follows:

1) Through full-screen measurement statistics, analyze the positive and negative pulse widths of each signal. If the pulse width of VSYNC and VHSYNC has abnormal values, it can be judged as a display anomaly caused by interference signals;

2) If the pulse width is normal, the number of cycles can be calculated through interval measurement statistics, analyzing the mutual containment relationship between signals of different sizes, and checking the timing parameters;

3) Through scaling mode and cursor measurement, analyze the delays between each timing signal.

ZDS4054 Plus Data Mining Oscilloscope

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