Comprehensive SoC Training Camp: Mastering Chip Design from A to Z

Comprehensive SoC v4.0 Chip Training

Lifetime mentorship and one-on-one coaching are the hallmarks of the SoC training camp!

Step-by-step guidance to help you build SoC from beginner to advanced, mastering architecture, algorithms, design, verification, DFT, and backend low power processes!

RegisterWeChat: 13541390811

The comprehensive SoC courses are as follows:

• SoC Design Video + Document + Practical + One-on-One Lifetime Mentorship (Free Video, No Time Limit)

• SoC Verification Video + Document + Practical + One-on-One Lifetime Mentorship (Free Video, No Time Limit)

• SoC Mid-level Video + Document + Practical + One-on-One Lifetime Mentorship (Free Video, No Time Limit)

• SoC Backend Video + Document + Practical + One-on-One Lifetime Mentorship (Free Video, No Time Limit)

Advanced Courses:

• 12nm 2.5GHz A72 Low Power DVFS Practical Training (Price less than half of competitors)

• DDR4/3 Project Practical Training (Price less than half of competitors)

The editor gradually publishes tutorials and knowledge of the entire chip design process on Knowledge Planet, including design, verification, DFT, backend knowledge, and a wealth of technical documents. If you, like me, crave knowledge and are not afraid of the explosion of knowledge in the entire process, you are welcome to join the discussion and study together for mutual progress!

The main business of Jingxin is design service + one-on-one chip mentoring training!

In addition, the editor’s team provides chip Design Service, including:

• Provides SoC, MCU, ISP, CIS chip design, verification, DFT design services

• Provides DDR/PCIE/MIPI/CAN/USB/ETH/QSPI/UART/I2C IP design

• Provides backend design for 7nm, 12nm, 28nm, 40nm, 55nm, 65nm, 90nm

• Provides customized chip design services for universities and enterprises, and design training business

The purpose of the Jingxin SoC v4.0 chip training camp:

Step-by-step guidance to help you master SoC algorithms, design, verification, DFT, and backend low power processes!

The Jingxin SoCv3.0 is a low-power multimedia SoC used for comprehensive chip training!

The Jingxin SoC system is divided into three levels of power management and integrates a low-power RISC-V processor, ITCM SRAM, DTCM SRAM, and integrates MIPI, ISP, USB, QSPI, UART, I2C, GPIO IP, using SMIC40 process for chip production.

(1) In the SoC design course, you will learn

• High-speed interface Verilog design implementation
• Image algorithm to RTL design implementation
• MIPI, ISP Verilog implementation and simulation
• Lint, CDC checks and UVM verification
• SoC subsystem C driver simulation
• Post-simulation

One course in design is equivalent to 5-6 courses at other training institutions, with a price of only 1/6

(2) In the SoC verification course, you will learn

• SoC subsystem UVM environment setup
• SoC subsystem UVC environment setup
• SoC subsystem VIP environment setup
• SoC subsystem DMA SRAM UVM joint verification
• SoC subsystem UART UVC verification
• SoC subsystem long packet, short packet, super long packet, glitch packet, header/footer error UVM verification

One course in verification is equivalent to 3-4 courses at other training institutions, with a price of only 1/6

(3) In the SoC mid-level course, you will learn

• DFT design (chip-level)
• Synthesis logic synthesis (chip-level)
• Low power UPF design, CLP technology

• Formal verification and other technologies

One mid-level course is equivalent to 4-5 courses at other training institutions, with a price of only 1/6

(4) In the SoC backend course, you will learn

• Low power design

• Layout routing (low power FF flow)
• StarRC/QRC
• STA/Tempus
• Power analysis
• DRC/LVS design

One backend course is equivalent to 3-4 courses at other training institutions, with a price of only 1/6

The course provides servers for practice! Taking you from algorithms, frontend, DFT to backend, participating in SoC project design. Please contact the author to register! Contact WeChat: 135-4139-0811

The data path for image processing in the Jingxin SoC training camp:

One-click completion of C code compilation, simulation, synthesis, DFT insertion, formal verification, layout routing, parasitic parameter extraction, STA analysis, DRC/LVS, post-simulation, formal verification, power analysis, and other processes. The upgraded chip design project V4.0 flow is as follows:

SoC one-click execution flow

MIPI DPHY+CSI2 Decoding

Classic designs in digital circuits: Implementation of multiple communication data Lane Merging

Classic designs in digital circuits: Implementation of multiple communication data Lane Distribution

Jingxin SoC Verification Architecture

The comprehensive chip verification architecture of Jingxin SoC:

A senior student from Jingxin told me that a master’s degree studying abroad in country X at a certain chip giant company has a salary of over 200,000 USD! Converted to RMB, it’s over 1,400,000, and he is only about 25 years old! Salary exceeds 1.4 million!

The editor checked Glassdoor’s salary:

The salary quotes for ASIC Engineers with 1-3 years of experience are around 212K USD, and 200K USD.

For ASIC Engineers with 7-9 years of experience, the salary quotes are around 311K USD, and 300K USD.

Of course, the specific salary also depends on each candidate’s level and job matching.

Education, project experience are very important, looking forward to more good news from Jingxin comrades! Stepping out of the country, the world is more exciting! The positive energy of the Jingxin SoC project is so great that I am shocked, I will continue to polish and help Jingxin comrades succeed together!

Jingxin SoC UPF Low Power Design

Full chip UPF low power design (including DFT design)

The Jingxin SoC training camp training project, before low power design, the power consumption is 27.9mW.

After low power design, the power consumption is 0.285mW, a reduction of 98.9%!

Voltage drop check:

Low power check:

The chip layout design V1.0

Chip layout design V2.0

Chip layout design V4.0

The DRC/LVS of low power design has extremely high practical value at the chip top level and is challenging! Unique experience sharing in the industry.

Rich tutorial documents

The Jingxin training camp has students asking how to add PAD to IO? Please consider how to achieve the best IO and PAD for Jingxin SoC?

SoC training camp VIP students ask why the low power cell is not inserted into the netlist?

While asking questions is encouraged, when we encounter problems, we should first think proactively and try to solve the problem ourselves. If we truly cannot solve it, we can seek help, as this leads to faster growth.

First, when I got this question, I opened the log, checking the log is a virtue of IC design! I found that after the EDA tool read in the UPF file, it reported the following warning, using many FF libraries.

The above image shows that the UPF specified voltage is 0.99V, while the CELL is 1.20V, causing the logical synthesis netlist to not insert MV CELL. Note that during synthesis, we used the SS library, so how could it be the FF library? I opened the constraint script and found the following bug:

So, I changed the constraint, replacing FF with SS. After running again, the result came out:

In the low power design section, I will leave a small bug inside the design, which is very simple. I will not disclose the answer; everyone must think more and run tests, as this will deepen your learning.

Students in the training program should note that the Jingxin SoC uses the always-on power domain voltage domain’s pwrdown_mux signal as the switch control signal for the power switch cell. However, there is a small issue in the design, not exactly a bug, but for the UPF low power flow, it is undoubtedly a bug!

Students in the training program should log in to the server to track the pwrdown signal and pay attention to its load situation. The RTL code is as follows:

Combining the netlist output from PR, we will do a CLP low power check, see the server for the script. It can be found that CLP reports an error saying that the switch control signal for the power switch cannot be found.

It must be said that CLP checks are crucial for low power and very important for chip design! The value of Jingxin SoC lies in connecting all these small knowledge points throughout the chip design process! What are you waiting for? Hurry up and register to join!

During the mid-process of chip design, the Jingxin SoC will insert isolation and other cells into the UPF constraints, but will not be able to insert power switch cells. Therefore, the control signal pwrdown_mux for the power switch cell will be optimized away (removed) if there is no load. Therefore, it is necessary to set the above MUX device as dont_touch or make pwrdown_mux a module port and prohibit auto_ungroup (and set no_boundary_optimization), so that this signal can be retained for the backend to implement power switch control. Students should complete the code modification based on the full flow environment and complete the following tasks:

1. Lint check, frontend simulation,

2. Complete mid-process and backend flow,

3. Complete CLP check, complete post-simulation

Students in the Jingxin training camp ask why some students finish the same floorplan quickly, while others encounter a lot of DRC issues (EDA tools keep iterating) leading to the tool being unable to finish? What could be the specific problem?

First, the editor discovered that the student defined TM2 as horizontal, while familiar students with Jingxin’s process know that TM2’s preference direction is VERTICAL.

Checking Jingxin’s LEF library file can also confirm:

How big of an impact does using the wrong direction have? Everyone should practice with the Jingxin SoC backend flow to find out through practice.

Students in the Jingxin training camp ask why PR took a whole day and night, 24 hours to complete routing but still had a lot of DRC errors? The editor has already minimized the design scale to speed up PR design. In fact, routing can be completed in 2 hours, why is it so slow? The reason is the routing of low power units. The specific reasons and solutions are welcome to join the Jingxin training camp for discussion.

The errors are mainly concentrated on M4, please think about how to solve it.

Students in the Jingxin training camp ask why the second PG pin (VDDG) of the power switch cell is connected from M1 instead of M2? Please think about what the problem is? How to solve it?

Students in the Jingxin training camp ask, how to handle LVS issues for Corner Pad?

After completing the frontend design simulation and DFT of the Jingxin SoC training, we come to the backend flow. This tutorial will teach you how to run the digital backend flow with one click.

The generation script command is as follows:

tclsh ./SCRIPTS/gen_flow.tcl -m flat all

Before generating the flow script, it is necessary to configure setup.tcl and other related parameters. Please refer to the unique self-developed Jingxin SoC frontend engineering, DFT engineering, and backend engineering, taking you from algorithms, frontend, DFT to backend to participate in SoC project design.

Students in the Jingxin training camp ask why Innovus reports an error reading the completed floorplan DEF file? First, check the log:

Reading floorplan file – ./data_in/DIGITAL_TOP.def (mem = 1595.0M).

#% Begin Load floorplan data … (date=10/23 22:38:01, mem=1579.3M)

**ERROR: (IMPFP-710): File version unknown is too old.

In the past EDI period, we could load the floorplan by defining fp_file:

set vars(fp_file) “./data_in/DIGITAL_TOP.def”

But now Innovus has upgraded and abandoned the fp_file loading method. Of course, you can also use the old version of EDI9.1 and earlier to include fp_file, then save it to create a new version, but this method is obviously unnecessary. Just as the log indicates, checking the log is a very good engineering habit.

Input floorplan file is too old and is not supported in EDI 10.1 and newer.

You can use EDI 9.1 and before to read it in, then save again to create new version.

The editor’s intuition tells me to first check which DEF version the student saved?

The student saved it as follows:

So how to solve it? Students are encouraged to join the Jingxin training camp for practice.

The Jingxin SoC uses many asynchronous FIFOs. Students interested in the asynchronous RTL implementation can extract the asynchronous FIFO to observe the layout wiring:

Check the area of all asynchronous FIFO cells;

dbget [dbget top.insts.pstatus unplaced -p].area

Check the names of all asynchronous FIFO cells:

dbget [dbget top.insts.pstatus unplaced -p].name

So how to extract the asynchronous path to observe the layout wiring? How to report timing? For more content, please refer to Knowledge Planet and SoC training camp.

That’s all for today’s sharing. If you, like me, crave progress and want to master the entire chip design process, please join my Knowledge Planet for rapid growth and mutual progress! Become a chip master as soon as possible!

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