

Image source: Internet
Image source: Internet
ARM DSU Application Example
Image source: Internet
Basic Composition of DSU
Image source: Internet
DSUAE Internal Framework Diagram of Cortex-A78AE
Image source: Internet
DSU AE mainly adds comparators, and the bright-colored parts are duplicated, including execution logic, clocks, power states, and various interfaces. However, the cache cannot be duplicated as that would be too costly and not very meaningful.
Image source: Internet
DSU-AE Separation Mode
Image source: Internet
DSU-AE Hybrid Mode
Image source: Internet
DSU-AE Interface
Image source: Internet
II. ARM’s on-chip bus
ARM Smart Driving Product Series
Image source: Internet
ARM CMN-700
Image source: Internet
ARM has developed a connection system between a bus and NoC, called CMN, primarily used to connect CPU cores, and can also connect CPU cores with accelerators. It adopts a MESH grid structure but lacks routing functionality; it is essentially still a bus, but the MESH grid supports many units, far exceeding a general bus, supporting up to 512 cores and 512MB of L3 cache, targeting the HPC market.
CMN-700 also supports AMBA AXI5, ACE5-lite, CXS, and CCIX
Related Reading
Understanding Automotive System-on-Chip SoC: Part 6: CPU Microarchitecture
Understanding Automotive System-on-Chip SoC: Part 5: Instruction Set and Computing Architecture
Understanding Automotive System-on-Chip SoC: Part 4: Cache, Superscalar, Out-of-Order Execution
Understanding Automotive System-on-Chip SoC: Part 3: ARM’s Business Model and Overview of CPU Microarchitecture
Understanding Automotive System-on-Chip SoC: Part 2: Automotive Chip Industry and Supply Chain
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