2016 Microcomputer and Applications Issue 3 Authors: Jing Desheng1,2, Gao Limin1, Guo Yuzhong1, Guo Xiaoguang1
Abstract: The missile-borne computer is the core component of missile control. To meet the requirements of the missile-borne computer regarding weight, power consumption, and reliability, a design method for a missile-borne computer using the SoC chip HKS6713 as the processor is proposed. The explanation is provided from both hardware design and software design perspectives, and key technologies such as program partition design, A/D acquisition result correction, and isolation protection during the development process are elaborated. This computer features small size, low power consumption, rich functionality, and ease of application, providing reference value for similar missile-borne computer designs. The designed missile-borne computer has undergone various tests and has been comprehensively tested in the system, meeting the performance requirements of the system and proving that this design is practical.
0 Introduction
SoC (System on Chip) is an integrated chip that focuses on embedded systems, pursuing maximum integration of product systems. The inherent single-chip characteristics of SoC can greatly improve system performance, reduce system cost, power consumption, and weight and size. With the development of electronic technology, SoC chips are widely used in the design of embedded computers.
The missile-borne computer［1，2］ is the core component of the missile, determining the success or failure of missile attack missions. The system requires a certain type of missile-borne computer to have functions such as cooperating with the fire control system to complete launch process control, collecting information from inertial combinations and components such as servos and guidance heads for guidance law calculations, and performing closed-loop control of the servo system. The types of external interconnection interfaces include GJB289A bus, RS422 bus, discrete input/output, and analog input/output. In response to the characteristics of multiple types of external interconnection interfaces, high precision requirements for analog acquisition, and strong real-time performance, this paper introduces a design method for a missile-borne computer with the domestic SoC chip HKS6713 as the processing core and focuses on key technical solutions in the design.
1 System Architecture
The missile-borne computer consists of hardware and software. The hardware includes four parts: processor module, discrete module, analog module, and power module. The processor module is used to implement control law calculations, RS422 asynchronous serial interface communication, GJB289A bus interface communication, etc., using SoC chip + CPLD design; the discrete module is used to collect signals such as warhead type identification signals, hatch opening signals, and power supply instructions; the analog module is used for A/D conversion and data latching, D/A conversion, etc.; the power module supplies power to other modules of the mission computer and external servo systems. The software includes initialization, analog input acquisition and output control, discrete input acquisition and output control, GJB289A bus transceiver control, and RS422 bus transceiver control, etc. The system architecture of the missile-borne computer is shown in Figure 1.
2 Hardware Design
2.1 Processor Module Design
The processor module is used for guidance law calculations and implementing functions such as GJB289A bus and RS422 asynchronous serial bus, including SoC chip HKS6713 processor and its peripheral circuits, power conversion circuits, reset circuits, memory circuits, RS232 and RS422 asynchronous serial interface circuits, GJB289A bus interface circuits, and board interconnect bus interfaces, etc.
HKS6713 is a large-scale SoC chip that integrates DSP core［3］, GJB289A protocol processor, 429 bus controller, CAN bus controller, multiple UART controllers, 64 KB dual-port memory, multiple interrupt control, servo counters, acceleration counters, odometer counters, switch input/output, and ADC acquisition functions, with a packaging form of CBGA601 and an operating temperature range of -55℃~+125℃. The processor module uses the DSP core, GJB289A protocol processor, dual-port RAM, and multiple UART controllers of the HKS6713 chip. The core of HKS6713 is compatible with TI’s TMS320C6713, containing program memory, data memory, direct memory access (DMA), POWER-DOWN logic, external memory interface (EMIF), MCBSP, MCASP, host interface, GPIO, and TIMER functions, with a system input clock frequency of 40 MHz, and the maximum working clock frequency after frequency doubling inside C6713 is 200 MHz. The chip has 256 KB of memory that can be used as program and data memory, of which 64 KB can be used as high-speed CACHE, allowing the processor to improve processing speed without frequent access to external memory when the capacity of user programs and data is less than 256 KB. The functional structure of HKS6713 is shown in Figure 2.
In the design, external Flash and SDRAM memory are configured for the SoC chip. The DSP core of the SoC chip is directly connected to the external memory through the EMIF bus, which directly supports asynchronous memory, SBSRAM, and SDRAM without the need for an external dedicated controller, and support for these memories can be achieved by configuring the EMIF registers. The DSP core has multiple external memory spaces［4］, each of which can be independently configured to support different types of memory, and the register settings can be used to establish read/write signal setup, gate, and hold times to adapt to various speeds of memory. In this design, a 16 MB Flash chip is configured as non-volatile memory to store programs and data that need to be retained after power-off. The external address space of the SoC chip can only directly access a maximum of 2 MB, so GPIO signals are used as the high-order address lines of the Flash chip, dividing the Flash space into 8 pages, with the program area and data area stored in different pages to improve storage safety. Considering that the internal RAM space of the DSP core is small (256 KB), part of which may need to be allocated for CACHE use, a 16 MB SDRAM is configured for the SoC chip.
The processor module significantly simplifies the circuit design by using the SoC chip HKS6713, requiring only the addition of corresponding transceivers, transformers, and other chips around the HKS6713 chip to complete the design of GJB289A bus and RS422 bus interfaces; data interaction functions are completed through the EMIF bus with SDRAM memory and Flash memory.
2.2 Discrete Module Design
The discrete module includes discrete input and discrete output sections, using a CPLD chip as the controller of the module, responsible for interconnection control with the processor module, reading the status of input discrete quantities, and determining the status of output discrete quantities.
To prevent mutual interference with other interconnection devices［5］, the missile-borne computer has adopted isolation protection designs for the discrete input/output circuits and RS422 serial circuits. The signals of the discrete input/output circuits belong to the 28 V power system, using opto-isolation; the RS422 bus transceiver nodes have restrictions on common-mode voltage, requiring common grounding. In the design, a five-wire system is used, with an isolation type DC/DC power conversion chip supplying power for the bus level converter, and the bus level converter is grounded with other nodes on the RS422 bus, while opto-isolators are used for isolation between the bus transceiver and protocol control, isolating the bus path from external interference. The design of the RS422 serial protection circuit is shown in Figure 3.
2.3 Analog Module Design
The analog module, under the control of the processor module, collects analog signals from the servo system and pressure sensors, outputting analog signals to control the servo control surfaces［6］. The A/D converter used in this design is simple and reliable but has a significant full-scale error (typical value ±0.38%). To improve A/D conversion accuracy and ensure system performance, a software method is employed to correct the A/D conversion results.
The ideal state conversion slope between the input and output of the A/D conversion chip is 1, as shown by the solid line in Figure 4, but due to the objective existence of gain error and offset error, the actual conversion slope deviates from 1, as shown by the dashed line in Figure 4. The slope k in Figure 4 can be calculated from the actual measured A/D conversion results, as shown in formula (1):
k=(y1-y2)/20（1）
The adjusted result is calculated by formula (2):
Ua=(Uts/k)-y0（2）
Where Ua is the adjusted result, Uts is the actual measured A/D conversion result, k is the slope of the A/D conversion result, and y0 is the error when the input is 0, i.e., conversion offset.
Since each conversion path in the A/D chip is independent, the slope k values are different. In the design, the k value of each path is calculated and stored in a designated location in the Flash memory. When collecting analog quantities, the software calls the corresponding conversion slope and offset error y0 of that path to obtain the corrected A/D conversion result. Through practical measurements, the range of A/D acquisition errors is reduced from -50 mV~+50 mV to -10 mV~+10 mV after correction, significantly improving accuracy and meeting system design requirements.
3 Software Design
The software of the missile-borne computer is used to implement system control and self-testing functions［7］. It includes collecting information from the aircraft’s fire control system, inertial components, servos, and guidance heads, performing guidance rate calculations, sending control information, and completing control of the missile’s flight posture, etc. In the design, considering the large amount of application program code, the application program code is divided into two categories: one category is non-time-critical code, such as ground testing, process control, and other function codes, which are moved to SDRAM memory for execution after power-on; the other category is time-critical code, such as flight control periodic tasks, which are moved to internal SRAM memory for execution after power-on. This solves the problem of insufficient space when all code is moved to internal SRAM memory and the problem of speed not meeting control cycle requirements when all is moved to external SDRAM memory.
4 Conclusion
This paper introduces a missile-borne computer design using the SoC chip HKS6713 as the processor, leveraging the advantages of the domestic SoC chip HKS6713, such as low power consumption, rich interfaces, and high reliability, meeting the missile-borne computer’s requirements in terms of performance, size, and processing capability, simplifying the difficulty of system design. The missile-borne computer produced according to this design scheme has undergone various tests with the system, and the tests have proven that the missile-borne computer can effectively complete the acquisition and control calculation tasks on the missile. Currently, missile control systems are widely used, and the missile-borne computer designed in this paper has high versatility and can be transplanted to other similar missile control systems at a very low cost.
References
［1］ Li Fanghui, Wang Fei, He Peikun. Principles and Applications of TMS320C6000 Series DSPs［M］. Beijing: Electronic Industry Press, 2005.
［2］ Liang Xiaogeng, Wang Borong, Yu Zhifeng, et al. Design of Air-to-Air Missile Guidance and Control System［M］. Beijing: National Defense Industry Press, 2006.
［3］ Zuo Qingqing, Liang Zhengzheng, Fan Xiufeng. Design of a Low-Cost Missile-Borne Computer［J］. Electronic Technology, 2015, 44(1): 57-59.
［4］ Xu Shaowei, Liu Shuo, Jing Desheng. Design and Implementation of Remote Software Loading Based on TMS320C6713B［J］. Aviation Computing Technology, 2013, 43(4): 122-123.
［5］ Tan Zhihong, Jing Desheng, Gao Limin. Design and Implementation of a High-Speed AD Acquisition System Based on DSP［J］. Electronic Technology, 2014, 42(4): 41-44.
［6］ Yu Jianchao, Yu Xiangbin, Li Qingliang, et al. Design of an Atmospheric Data Computer Inspection Instrument Based on Embedded Computers［J］. Microcomputer and Applications, 2014, 33(17): 92-94.
［7］ Lin Yingying, Gao Hong, Zhang Mingshan, et al. Design of an Embedded QR Code Data Wireless Multi-Point Transmission System［J］. Microcomputer and Applications, 2014, 33(21): 48-50, 53.
