Comprehensive Analysis of FPGA Basics

FPGA (Field Programmable Gate Array) is a type of field programmable gate array that has evolved from programmable devices such as PLA, PAL, GAL, and CPLD. It serves as a semi-custom circuit in the domain of Application-Specific Integrated Circuits (ASIC), addressing the shortcomings of custom circuits while overcoming the limitations of existing programmable devices in terms of the number of logic gates.

1. Introduction to FPGA

FPGAs are widely used to implement digital circuit modules, allowing users to reconfigure the internal logic and I/O modules of the FPGA to meet their needs. They also feature static reprogrammability and dynamic in-system reconfiguration, enabling hardware functions to be modified through programming, similar to software. It is no exaggeration to say that FPGAs can perform the functions of any digital device, ranging from simple 74 series circuits to high-performance CPUs, all achievable with FPGAs. An FPGA is like a blank canvas or a pile of building blocks, where engineers can freely design a digital system using traditional schematic entry methods or hardware description languages.

2. History of FPGA Development

The development history of FPGAs is illustrated in the figure below. Compared to PROM, PAL/GAL, and CPLD, FPGAs offer larger scale and higher performance.

Figure 1: History of FPGA Development

Major manufacturers of FPGA chips include Xilinx, Altera, Lattice, and Microsemi, with the first two holding a combined market share of 88%. Currently, all mainstream FPGA manufacturers are based in the United States. Domestic FPGA manufacturers have started their R&D at least 20 years later than their American counterparts and are still in the growth stage, limited to low-end products, with no mature applications in the communication market.

In December 2015, Intel acquired Altera for $16.7 billion. Shortly after the acquisition, Altera established a product roadmap for integrating Intel processors with FPGAs. The benefits of integrating these two products include providing innovative heterogeneous multicore architectures to meet the demands of new markets such as artificial intelligence while significantly reducing power consumption.

Figure 2: Application History of FPGA in Telecommunications

FPGAs have very mature and widespread applications in aerospace, military, and telecommunications fields. For example, in the integrated telecommunications equipment phase, FPGAs are applied in network protocol parsing and interface conversion due to their programming flexibility and high performance.

In the NFV (Network Function Virtualization) phase, FPGAs achieve a fivefold performance improvement for network element data planes based on general-purpose servers and hypervisors, while being managed and orchestrated by the general-purpose OpenStack framework.
In the cloud era, FPGAs have been used as basic IaaS resources to provide development and acceleration services in public clouds, with AWS, Huawei, and BAT offering similar general services.
As of now, Intel’s Stratix 10 devices have been successfully applied in Microsoft’s real-time AI cloud platform, Brainwave.

3. Recent Developments of Two Major FPGA Companies

Xilinx focuses on chip leadership and a rich array of acceleration solutions, securing support from mainstream cloud platforms through an open strategy, establishing its leading position in data centers. Its UltraScale+ series FPGAs are more than a year ahead of competitors, giving it an advantage in cloud platform competition, with its VU9P devices being widely used in cloud computing platforms of companies including AWS, Baidu, Ali, Tencent, and Huawei.

To meet the growing performance demands for FPGA chips in the accelerator field, Xilinx has released the next-generation ACAP chip architecture aimed at data centers and launched the 7nm Everest devices. This device no longer falls under traditional FPGA categories; it integrates ARM, DSP, and Math Engine processor arrays and is expected to enter mass production in 2019. Compared to VU9P, Everest is expected to enhance AI processing performance by 20 times.

Intel, on the other hand, provides a full-stack solution from hardware to platform to application, avoiding open hardware and platform designs to prevent ecosystem fragmentation. While Intel has made significant investments, progress has been slow.

Figure 3: Xilinx Product Series

Figure 4: Intel (Taking the Stratix Series as an Example) Product Process Era

In practical applications of FPGAs in the data center server market, there are certain technical challenges, including the following:

1. High programming threshold: Hardware description languages differ from software development languages, requiring developers to have a deep understanding of underlying hardware; thus, talent becomes a significant limiting factor for FPGA applications. It is estimated that there are currently around 20,000 people engaged in FPGA development in China.
2. High integration difficulty: FPGA development and application require collaboration between software and hardware, including system modeling using high-level languages, hardware coding (circuit) design, hardware code simulation, and joint debugging of low-level driver software with hardware logic.
3. Longer development cycle compared to software: Hardware development is more complex than software development, leading to longer debugging cycles.
4. Difficulty in obtaining independent logic IP.

4. Overall Structure of FPGA

The architecture of an FPGA mainly includes Configurable Logic Blocks (CLB), Input Output Blocks (IOB), interconnects, and other embedded units.

CLB is the basic logic unit of an FPGA. The actual number and characteristics vary depending on the device, but each CLB contains a configurable switch matrix composed of 4 or 6 inputs, several selection circuits (multiplexers, etc.), and flip-flops. The switch matrix has a high degree of flexibility and can be configured to handle combinational logic, shift registers, or RAM.

FPGAs support many I/O standards, providing ideal interface bridging for system design. The I/Os within an FPGA are grouped by banks, with each bank capable of independently supporting different I/O standards. Currently, the most advanced FPGAs offer more than ten I/O banks, enabling flexible I/O support.

CLBs provide logic performance, while flexible interconnect wiring is responsible for transmitting signals between CLBs and I/Os. There are several types of wiring, from those designed specifically for CLB interconnections (short-line resources) to high-speed horizontal and vertical long lines within the device (long-line resources), and to global low-skew wiring for clocks and other global signals (global dedicated wiring resources). Generally, design software from manufacturers hides the interconnect wiring tasks, making it largely invisible to users, significantly reducing design complexity.

Embedded hard cores include RAM, DSP, DCM (Digital Clock Management module), and other specific interface hard cores. The internal structure of FPGA devices is illustrated in the diagram below.

Figure 5: Internal Structure of FPGA Devices

Generally, the larger the numerical designation of a device, the greater the logic resource scale it can provide. When selecting FPGA devices, users need to refer to this table and consider multiple aspects of their project, including logic resources (CLB), internal BlockRAM, interfaces (number of high-speed Serdes), digital signal processing (number of DSP hard cores), and future expansion needs to determine the most suitable logic device for their project.

5. FPGA Development Process

The FPGA design process involves using EDA development software and programming tools to develop FPGA chips. The FPGA development process generally includes the following main steps: functional definition/device selection, design input, functional simulation, logic synthesis, layout and routing, and programming/debugging.

1. Functional Definition/Device Selection: Before starting an FPGA design project, a system function definition and module division must be established. Additionally, based on task requirements such as system functionality and complexity, trade-offs must be made regarding working speed, device resources, costs, and the feasibility of wiring to select appropriate design solutions and device types.

2. Design Input: Design input refers to expressing the designed system or circuit using hardware description languages. The most commonly used hardware description language is Verilog HDL.

3. Functional Simulation: Functional simulation refers to the logical function verification of the circuit designed by the user before logic synthesis. Before simulation, a testing platform needs to be built, and testing stimuli prepared. The simulation results will generate report files and output signal waveforms, allowing observation of signal changes at various nodes. If errors are found, the design must be modified. Common simulation tools include ModelSim from Model Tech and VCS from Synopsys.

4. Logic Synthesis: Logic synthesis is the process of transforming higher-level abstract descriptions into lower-level descriptions. Synthesis optimization optimizes the generated logical connections according to objectives and requirements, flattening the hierarchical design for implementation by FPGA layout and routing software. At the current level, synthesis optimization refers to compiling design inputs into logic connection netlists composed of basic logic units such as AND gates, OR gates, NOT gates, RAM, and flip-flops, rather than real gate-level circuits.

The actual gate-level circuits need to be generated using the layout and routing capabilities of FPGA manufacturers based on the synthesized standard gate-level structure netlist. To convert to a standard gate-level structure netlist, the HDL program must conform to the style required by specific synthesizers. Common synthesis tools include Synplicity’s Synplify/Synplify Pro software and synthesis development tools released by various FPGA manufacturers.

5. Layout and Routing Implementation: Layout and routing can be understood as using implementation tools to map logic onto the resources of the target device structure, determining the optimal layout for logic, selecting routing channels for linking logic with input/output functions, and generating corresponding files (such as configuration files and reports); implementation involves configuring the logic netlist generated from synthesis onto specific FPGA chips. Since only FPGA chip manufacturers have the best understanding of chip structures, layout and routing must utilize tools provided by chip developers.

6. Programming and Debugging: The final step of the design is programming and debugging. Chip programming refers to generating data files (bitstream generation) that load programming data into the FPGA chip; testing can then begin on the board. Finally, the FPGA file (such as .bit file) is downloaded from the computer to the FPGA chip on the board.

6. How to Use FPGA

Once the FPGA development is complete, the validated loading file can be obtained. After outputting the loading file, normal business processing and verification can begin (describing the entire process using software loading methods).

1. Logic loading;
2. After loading logic onto the board, it is necessary to reset the logic;
3. After the reset is complete, the software must wait for a period until the logic phase-locked loop stabilizes;
4. The software initiates self-check operations for the logic’s external RAM, internal Block RAM, DDRC, etc.;
5. After the software completes the self-check, it initializes all writable RAM spaces and registers of the logic;
6. After initialization is complete, the software configures items and registers according to the logic chip manual;
7. Once the logic is ready, business processing can begin.

7. Suitable Scenarios for FPGA

FPGAs are suitable for irregular, highly concurrent, intensive computation, and protocol parsing processing scenarios, such as artificial intelligence, gene sequencing, video encoding, data compression, image processing, and network processing across various fields.

The above content is sourced from Intelligent Computing Chip World, author Hao Zai.

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