FPGA (Field Programmable Gate Array) refers to a field-programmable gate array. It is a product developed further based on programmable devices such as PLA, PAL, GAL, and CPLD. It serves as a semi-custom circuit in the domain of Application-Specific Integrated Circuits (ASIC), addressing the shortcomings of custom circuits and overcoming the limitations of the number of gate circuits in existing programmable devices.
1. Introduction to FPGA
FPGA is widely used for implementing digital circuit modules, allowing users to reconfigure the internal logic and I/O modules of the FPGA to meet their needs. It also features static reprogrammability and dynamic in-system reconfiguration, enabling hardware functions to be modified through programming like software. It is no exaggeration to say that an FPGA can perform any function of a digital device, from simple 74 circuits to high-performance CPUs, all can be realized using FPGA. FPGA is like a blank sheet of paper or a pile of building blocks, where engineers can freely design a digital system using traditional schematic input methods or hardware description languages.
2. History of FPGA Development
The development history of FPGA is illustrated in the following figure. Compared to PROM, PAL/GAL, and CPLD, FPGA has a larger scale and higher performance.
Figure 1: History of FPGA Development
Mainstream FPGA chip manufacturers include Xilinx, Altera, Lattice, and Microsemi, with the first two companies holding a combined market share of 88%. Currently, all mainstream FPGA manufacturers are American companies. Domestic FPGA manufacturers, having started research and development at least 20 years later than the US, are still in the growth stage, limited to the low-end market, and have not yet achieved mature applications in the communication market.
In December 2015, Intel spent $16.7 billion to acquire Altera. Shortly after the acquisition, Altera established a product roadmap for integrating Intel processors with FPGAs. The benefit of integrating these two products is that it can provide innovative heterogeneous multi-core architectures to meet the needs of new markets such as artificial intelligence while significantly reducing power consumption.
Figure 2: Application History of FPGA in Telecommunications
FPGA has very mature and widespread applications in aerospace, military, and telecommunications fields. For example, in the telecommunications equipment integration phase, FPGA is used for network protocol parsing and interface conversion due to its programming flexibility and high performance.
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In the NFV (Network Function Virtualization) phase, FPGA achieves a 5-fold performance improvement for network element data planes based on general-purpose servers and hypervisors, while being managed and orchestrated by the general OpenStack framework.
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In the cloud era, FPGA has been used as a basic IaaS resource to provide development and acceleration services in public clouds, with AWS, Huawei, and BAT offering similar general services.
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As of now, Intel’s Stratix 10 devices have been successfully applied to Microsoft’s real-time artificial intelligence cloud platform, Brainwave project.
3. Recent Developments of Two Mainstream FPGA Companies
Xilinx focuses on chip leadership and rich acceleration solutions, gaining support from mainstream cloud platforms through an open strategy, establishing its leading position in data centers. Its UltraScale+ series FPGA leads competitors by more than a year, giving it a competitive edge in cloud platform competition, with its VU9P devices being widely used in cloud computing platforms of several companies including AWS, Baidu, Ali, Tencent, and Huawei.
To meet the increasing performance demands for FPGA chips in the accelerator field, Xilinx has released the next-generation ACAP chip architecture for data centers and launched the 7nm Everest device. This device no longer belongs to traditional FPGA; it integrates ARM, DSP, Math Engine processing arrays, and will be mass-produced in 2019. Compared to VU9P, the AI processing performance supported by Everest will be increased by 20 times.
Intel, on the other hand, provides a full-stack solution from hardware to platform to applications, avoiding open hardware and platform designs to prevent ecosystem fragmentation. Although it has invested heavily, progress has been slow.
Figure 3: Xilinx Product Series Diagram
Figure 4: Intel Product Process Years (Taking Stratix Series as an Example)
In the actual application of FPGA in the data center server market, there are certain technical challenges, specifically including the following aspects:
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1. High programming threshold: Hardware description languages differ from software development languages, requiring developers to have a deep understanding of the underlying hardware; thus, talent becomes an important limiting factor for FPGA applications. It is estimated that there are currently about 20,000 people engaged in FPGA development in China.
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2. High integration difficulty: FPGA development and application require the collaboration of software and hardware, including system modeling using high-level languages, hardware code (circuit) design, hardware code simulation, and debugging of low-level driver software with hardware logic.
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3. Longer development cycle compared to software: Hardware development is more complex than software development, leading to longer debugging cycles.
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4. Difficulty in obtaining independent logic IP.
4. Overall Structure of FPGA
The architecture of FPGA mainly includes Configurable Logic Blocks (CLB), Input Output Blocks (IOB), internal interconnects, and other embedded units.
CLB is the basic logic unit of FPGA. The actual quantity and characteristics may vary depending on the device, but each CLB contains a configurable switch matrix composed of 4 or 6 inputs, several selection circuits (multiplexers, etc.), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinational logic, shift registers, or RAM.
FPGA supports many I/O standards, providing ideal interface bridging for system design. The I/O within FPGA is grouped by banks, with each bank capable of independently supporting different I/O standards. Currently, the most advanced FPGAs offer more than a dozen I/O banks, providing flexible I/O support.
CLB provides logic performance, while flexible interconnect wiring is responsible for transmitting signals between CLB and I/O. There are several types of wiring, from those designed specifically for CLB interconnections (short-line resources) to high-speed horizontal and vertical long lines within the device (long-line resources), to global low-skew wiring for clocks and other global signals (global dedicated wiring resources). Generally, design software from manufacturers hides the interconnect wiring tasks, making it significantly easier for users.
Embedded hard-core units include RAM, DSP, DCM (Digital Clock Management Module), and other specific interface hard cores. The internal structure of FPGA devices is illustrated in the following diagram.
Figure 5: Internal Structure Diagram of FPGA Devices
Generally speaking, the larger the device model number, the greater the logic resource scale that the device can provide. When selecting FPGA devices, users need to refer to this table and comprehensively consider the project’s most suitable logic device based on various needs such as logic resources (CLB), internal BlockRAM, interfaces (number of high-speed Serdes), digital signal processing (number of DSP hard cores), and future expansion.
5. FPGA Development Process
The design process of FPGA involves using EDA development software and programming tools to develop the FPGA chip. The typical FPGA development process is illustrated in the following figure, including the main steps of function definition/device selection, design input, functional simulation, logic synthesis, layout and routing implementation, and programming debugging.
1. Function definition/device selection: Before starting an FPGA design project, the system functionality must be defined, and modules must be divided. Additionally, based on task requirements, such as system functionality and complexity, trade-offs must be made regarding working speed, device resources, costs, and wiring feasibility to choose suitable design schemes and device types.
2. Design input: Design input refers to using hardware description languages to express the designed system or circuit in code. The most commonly used hardware description language is Verilog HDL.
3. Functional simulation: Functional simulation refers to verifying the logical functionality of the designed circuit before logic synthesis. Before simulation, a test platform must be set up and test stimuli prepared. The simulation results will generate report files and output signal waveforms, from which changes in signals at various nodes can be observed. If errors are found, the design must return to modify the logic design. Common simulation tools include ModelSim from Model Tech and VCS from Synopsys.
4. Logic synthesis: Synthesis refers to transforming higher-level abstract descriptions into lower-level descriptions. Synthesis optimization optimizes the generated logic connections according to goals and requirements, flattening hierarchical designs for FPGA layout and routing software implementation. At the current hierarchy level, synthesis optimization refers to compiling design inputs into a logic connection netlist consisting of basic logic units such as AND gates, OR gates, NOT gates, RAM, and flip-flops, rather than a real gate-level circuit.
The real specific gate-level circuit needs to utilize the layout and routing capabilities of FPGA manufacturers to generate based on the standard gate-level structure netlist produced after synthesis. To convert to a standard gate-level structure netlist, the HDL program must be written in accordance with the style required by the specific synthesizer. Common synthesis tools include Synplicity’s Synplify/Synplify Pro software and various synthesis development tools released by each FPGA manufacturer.
5. Layout and routing implementation: Layout and routing can be understood as using implementation tools to map logic to the resources of the target device structure, determining the optimal layout for the logic, selecting routing channels for connecting logic with input/output functions, and generating corresponding files (such as configuration files and related reports); implementation involves configuring the synthesized logic netlist onto the specific FPGA chip. Since only FPGA chip manufacturers have the best understanding of chip structure, layout and routing must use tools provided by chip developers.
6. Programming debugging: The final step of design is programming debugging. Chip programming refers to generating the data file used (bitstream generation) and loading the programming data into the FPGA chip; after that, board testing can begin. Finally, the FPGA file (such as .bit file) is downloaded from the computer to the FPGA chip on the board.
6. How to Use FPGA
Once FPGA development is completed, the validated loading file is obtained. After outputting the loading file, normal business processing and validation can begin (taking software loading as an example to describe the entire process).
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1. Logic loading;
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2. After loading the logic, the board software needs to reset the logic;
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3. After the reset is completed, the software needs to wait for a period until the logic phase-locked loop stabilizes;
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4. The software performs self-check operations on the logic’s external RAM, internal Block RAM, DDRC, etc.;
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5. After the software completes self-checking, it initializes all writable RAM spaces and registers of the logic;
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6. After initialization is completed, the software configures items and registers according to the logic chip manual;
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7. The logic is ready and can begin processing business.
7. FPGA Applicable Scenarios
FPGA is suitable for irregular multi-concurrency, intensive computing, and protocol parsing processing scenarios, such as artificial intelligence, gene sequencing, video encoding, data compression, image processing, and network processing in various fields.
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