Parallel programming, the earliest programming method, is the most powerful, but requires connecting more pins, usually needing a high voltage of 12V~24V for distinction, referred to below as high voltage parallel programming.
ISP (In System Programmability) is in-system programming, abbreviated as serial download.
IAP (In Application Programming) refers to application programming, similar to BootLoader.
1 Although ISP utilizes the SPI interface pins (except for M64/M128 which use the UART0 interface, and Tiny13 which has no SPI interface), it only works at reset, and a qualified downloader will automatically disconnect the port after the download is complete, having no effect during normal operation (the downloader will definitely not remain connected in product applications).
2 Although high voltage parallel downloading can fix any fuse bit, it is impractical for chip packages, so the ISP interface is the most commonly used downloading method.
3 Although IAP is a new upgrading method, the IAP program itself must first be burned into the chip using high voltage parallel download or ISP.
4 Chips like Tiny13, which have very few pins, have ISP but no [high voltage parallel programming] and are specially designed for [high voltage serial programming].
Therefore, products generally leave an ISP interface socket, or to save space, just leave 6 pads.
Conditions for ISP operation
1 The chip has no physical damage.
2 The chip’s SPIEN fuse bit = 0 enables ISP functionality.
3 The chip’s RSTDISBL fuse bit = 1 keeps the RESET pin effective (if the chip has this fuse bit).
4 The wiring is normal ——— wrong connection? Short circuit?
5 The downloader is normal ——- especially consider the issue of poor contact in connections.
6 Power supply
Operating clock ISP clock (must be less than 1/4 of the operating clock)
4096Hz 1024Hz // a very peculiar usage, external 32.768KHz crystal + CKDIV8, but AVRISP still provides a speed of 603Hz.
// Another simple solution is to connect a 1MHz crystal in parallel with the 32.768KHz crystal during downloading; the dual dragon download line is equipped with an 8MHz quartz crystal.
32768Hz 8192Hz
128KHz 32KHz // internal RC128KHz
1.0MHz 250KHz // default value (including 8MHz + CKDIV8), so the ISP speed of AVRISP is mostly 230KHz.
8.0MHz 2000KHz
16.0MHz 4000KHz
The operating clock does not equal the oscillator frequency because some AVR chips have a system clock prescaler that can divide the oscillator by 1~256.
The CKDIV8 fuse bit determines the initial value of the CLKPS bit.
If CKDIV8 is not programmed, the CLKPS bit resets to “0000”; if CKDIV8 is programmed, the CLKPS bit resets to “0011”, giving a startup division factor of 8.
ISP clock provided by AVRISP: 921.6KHz, 230.4KHz, 57.6KHz, 28.8KHz, 4.0KHz, 603Hz.
ISP clock provided by STK500: 1.845MHz, 460.8KHz, 115.2KHz, 57.6KHz, 4.0KHz, 1206Hz.
Clock setting ISP scheme
Internal RC select appropriate ISP speed.
External RC connect appropriate resistance and capacitance, select appropriate ISP speed. —— Remedy: Connect external clock source to XTAL1.
External RC is generally meaningless as frequency accuracy/stability is low, and costs are not reduced, so new AVR chips no longer have this option.
Users should note the remedy methods after erroneous settings.
External crystal connect appropriate crystal, select appropriate ISP speed. —— Remedy: Connect external clock source to XTAL1.
External clock connect appropriate clock source, select appropriate ISP speed. —— Remedy: Connect external clock source to XTAL1.
External clock source can be an external (4MHz) active crystal output, XTAL2 pin of other MCUs, various square wave oscillator circuits (NE555) output, etc.
Most AVR chips’ ISP ports are SCK, MOSI, MISO, RESET.
While the ISP ports of M64/M128 are SCK, PDI, PDO, RESET.
Moreover, M64/M128 is factory default compatible with M103—- fuse bit M103C=0, many new features cannot be used, and programs may not run normally.
—- Because C compilers usually automatically point SP to the end of SRAM, M103=0x0FFFH, M64/M128=0x10FFH, which will inevitably cause errors!
All fuse bits of AVR are:
1 Unprogrammed, mostly means inactive.
0 Programmed, mostly means active.
This is true for all programmable technologies:
PROM/EEPROM/FLASH are all set to all 1s (0xFF) at factory and after erasure, and must be programmed to change to 0.
Conversely, just like CE/OE/INT are [active low], this is also very common.
In ISP mode, the SPIEN bit can never be accessed (modified), which is a hardware protection of the AVR chip.
M16/M32/M64/M128, which have an independent RESET pin, will not disable ISP in ISP mode. Regardless of how the fuse bits are modified, normal operation can be restored.
M8/M48/M88/M168/Tiny series have RSTDISBL fuse bits that can cause RESET to fail and make ISP inoperative; in other cases, normal operation can be restored.
Generally, as long as the conditions for ISP operation are met, and XTAL1 is connected to the output of a 4MHz active crystal, it is basically foolproof.
Do not forget that the clock signal for parallel high voltage programming is also introduced from the XTAL1 square wave signal.
If the active crystal method does not work (except for ISPEN=0, RSTDISBL=0 cases), high voltage programming may also not be effective.
Impact of JTAG (M16, M32, M128, etc.):
JTAG can access SPIEN and JTAGEN; if both are accidentally set to SPIEN=1, JTAGEN=1, the MCU will be locked, requiring high voltage parallel programming to recover.
Impact of DebugWIRE: (M48, M88, M168, T2313, etc., the data sheet is not very detailed)
Since DebugWIRE uses the RESET pin for communication, it conflicts with ISP.
DebugWIRE functionality can be enabled via ISP or high voltage parallel programming [i.e., DWEN=0]; enabling DebugWIRE functionality will disable ISP functionality.
DebugWIRE can be used to disable DebugWIRE functionality [i.e., DWEN=1]; after disabling DebugWIRE functionality, if RSTDISBL=1, SPIEN=0, ISP functionality is valid.
Notably, during DebugWIRE debugging, the use of breakpoints will reduce Flash data retention time; devices used for DebugWIRE debugging cannot be sent to end customers.
JTAG MKII simultaneously possesses JTAG/DebugWIRE/ISP functionalities, allowing easy switching between DebugWIRE/ISP.
(Software needs to be upgraded to version 1.09 or later, corresponding to AVRstudio version 4.12 or later)
Latest version JTAG MK2 user manual (Chinese PDF) (20051125)
When designing systems using DebugWIRE, the following checks must be performed:
• The pull-up resistor for dW/(RESET) must not be less than 10kΩ. DebugWIRE does not require a pull-up resistor.
• Directly connecting the RESET pin to VCC will not work.
• When using DebugWIRE, the capacitor connected to the RESET pin must be disconnected.
• All external reset sources must be disconnected.
