1. Assumptions and Constraints
Master CPU
|
MASTER CPU |
SLAVE CPU |
||
|
Master CPU Model |
Infineon TC275TP |
Slave CPU Model |
Freescale MM9Z1_638 |
|
Hardware Constraints |
PFLASH: 4M Byte, Data Flash: 384K Byte, DSPR: 120K Byte, PSPR: 20K Byte |
Hardware Constraints |
Flash: 128 kByte, RAM: 8.0 kByte, EEPROM: 4.0 kByte |
|
Memory Consumption |
Overall usage ≤ 80%, for stack: Normal operation ≤ 70%, Stress test ≤ 85% |
Memory Consumption |
Overall usage ≤ 80%, for stack: Normal operation ≤ 70%, Stress test ≤ 85% |
|
CPU Load Constraints |
Normal operation ≤ 70%, Stress test ≤ 85% |
CPU Load Constraints |
Normal operation ≤ 70%, Stress test ≤ 85% |
|
Software Runtime Environment Constraints |
Running in RTOS environment, using AUTOSAR compliant operating system RTA-OS |
Software Runtime Environment Constraints |
No RTOS front and back-end running environment |
|
Timing Constraints |
In RTOS environment, each task execution timeout error ≤ 5%, functional safety requirement related task execution timeout error ≤ 2% |
Timing Constraints |
In front and back-end running environment, each periodic function call execution timeout error ≤ 5%, functional safety requirement related periodic function call execution timeout error ≤ 2% |
2. Compile EnvironmentMaster CPU: TASKING VX-toolset for TriCore v4.2r2Slave CPU: CodeWarrior Development Studio for Microcontrollers v10.71). Software Architecture Design2).Software Architecture Overview3). Software Architecture Diagram (Slave CPU)
3. Layer & Module Definition (Slave CPU)
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