“ In the wave of AI and high-performance computing, a single chip can no longer meet the dual demands of computing power and energy efficiency. Heterogeneous computing and Chiplet multi-chip integration are gradually becoming core trends in the semiconductor industry. The Multi-Die interconnect solution launched by Arteris allows multiple RISC-V chips to work together as if they were a single chip, significantly reducing system complexity and enhancing performance. This is not only a transformation in chip design methodology but also opens up new possibilities for RISC-V in key application scenarios such as AI, automotive, and data centers in the future.“
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Qinheng Micro IPO: From Qinheng Core to Science and Technology Innovation Board Inquiry
Nanjing Qinheng Microelectronics (Qinheng Micro) is moving towards an IPO on the Science and Technology Innovation Board, with its stock review status changed to “inquiry.” Since its establishment in 2004, the company has followed a unique path of independent IP development—abandoning reliance on third-party IP, focusing on underlying key technologies, and gradually building an independent IP system of “Qinheng core + USB/Bluetooth/Ethernet interfaces,” accumulating a large number of patents and layout design rights.
This development path of “exchanging time for technology,” although requiring significant investment, has resulted in achievements such as “over 100 million shipments of Qinheng RISC-V cores,” and has to some extent realized a commercial closed loop for self-developed technologies. However, the company also faces market and governance risks such as competition from global giants, declining gross margins, and inventory backlog; additionally, the actual controller Wang Chunhua controls 94.57% of the shares through a multi-layered equity structure, which, while beneficial for decision-making, may also bring governance concerns.
Sticking to the independent research and development route for twenty years demonstrates the long-termism of domestic RISC-V.
Original link on 36Kr platform:
https://eu.36kr.com/en/p/3440449308432776
02
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Highlights of New Features in RISC-V (QEMU 10.1)
QEMU 10.1 brings several key improvements to RISC-V simulation: new support for atomic instruction fetching (Ziccif), Svrsw60t59b extension, and max_satp_mode for host CPUs; enhanced ACPI support for virtual machines (including ACPI from RIMT to virt machines); added support for the Open Chip Institute–Kunming Lake CPU and platform, as well as a setting for the vsetvli instruction to retain the VILL bit attribute, and an entry for riscv_hwprobe in the linux-user strace list. Along with a series of fixes and optimizations for vector instructions, PMP (Physical Memory Protection) region configurations, CSR migration boundaries, this update significantly enhances the compatibility and stability of RISC-V virtualization.
Original link:https://9to5linux.com/qemu-10-1-released-with-tdx-support-many-risc-v-and-arm-improvements
03
DietPi Compatibility Enhancements on RISC-V Architecture
The lightweight Linux distribution DietPi v9.16 has been released, bringing better support for RISC-V architecture. The new version not only synchronizes with Debian Trixie but also optimizes the APT update process, significantly improving installation and upgrade speeds. On the RISC-V platform, users can now run applications like Snapcast and Docker Compose more smoothly, which means the RISC-V community is gaining more native support for mainstream tools and ecosystem software. For developers, this step makes building the RISC-V development environment lighter and more efficient.
Original link:https://news.ycombinator.com/item?id=45044229
04
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Heterogeneous Computing: From “Multi-Core Stacking” to “Efficient Collaboration”
At the Andes RISC-V CON Silicon Valley held in April 2025, Imagination Technologies and Baya Systems showcased a vivid and practical demonstration: they simulated and analyzed system behavior under CPU, GPU, and hybrid configurations using the WeaverPro CacheStudio tool, presenting the inherent challenges and thought paths of true heterogeneous platform design.
Core insights include:
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Performance bottlenecks are not in computing power, but in “data feeding”: no matter how many computing resources there are, they must rely on efficient data movement, synchronization, and cache sharing to drive performance.
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Fine-grained cache modeling insights performance: the combination of cache capacities from L1 to L3 has a profound impact on hit rates, data reuse, and latency; for example, under a certain combination, the L2 cache hit rate is only 45%, and bottlenecks can be quickly identified through modeling.
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Heterogeneous design requires collaborative optimization: architecture must consider not only the additive effects of different processing units but also overall refinement in data flow, scheduling strategies, cache consistency, and memory layout.
A truly efficient heterogeneous system is not about having more cores, but starting from “feeding capacity” and ensuring collaborative efficiency and performance through early system-level tuning.
Original link:https://semiengineering.com/unleashing-heterogeneous-compute-lessons-from-real-world-system-design/
05
Heterogeneous Computing Era: Arteris Multi-Die Builds a High-Speed Bridge for RISC-V
The Multi-Die interconnect solution launched by Arteris aims to address connection efficiency and consistency issues during the transition of RISC-V SoCs to chiplet multi-chip modular design.
Its key advantages include:
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Cache Coherent Ncore NoC technology breaks chip boundaries, maintaining cache consistency between multiple dies (chips), allowing application software to perceive them as a single chip execution seamlessly.
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It is also compatible with FlexNoC and other non-consistent communication protocols, supporting mainstream die-to-die interface standards like UCIe, ensuring high bandwidth, low latency concurrency, high performance, and high energy efficiency.
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This solution simplifies the integration process through automation tools, accelerating SoC design progress and providing a solid connection foundation for hardware innovation in RISC-V for new era applications such as AI, HPC, and automotive electronics.
Arteris’s Multi-Die solution provides an efficient and reliable “high-speed bridge” for modular RISC-V chip design through standardized, scalable, and cache-coherent network interconnects, taking a crucial step towards the AI and high-performance era.
Original link:https://www.arteris.com/blog/arteris-multi-die-solution-for-the-risc-v-ecosystem/
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