H-JTAG

JTAG Interface Design (5) – JTAG-2

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JTAG Interface Design (5) - JTAG-2

Previously, we discussed the hardware form and basic principles of JTAG. This article uses a JTAG VIP simulation to interpret the waveforms. Referencing SOC Design (4) – Using S Company’s VIP, we first generate an example for JTAG testing: dw_vip_setup -path /home/designware/run_jtag -example jtag_svt/tb_jtag_svt_uvm_basic_sys Enter the simulation directory with cd run_jtag/examples/sverilog/jtag_svt/tb_jtag_svt_uvm_basic_sys, and type in: gmake … Read more

Comparison of Embedded Debug Interfaces JTAG and SWD

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Comparison of Embedded Debug Interfaces JTAG and SWD

Developing and debugging embedded systems is a complex task that requires powerful tools and interfaces to ensure the correctness of hardware and software. In this field, JTAG (Joint Test Action Group) and SWD (Serial Wire Debug) are two commonly used debugging interface standards that play a crucial role in embedded system development. This article will … Read more