Anyone familiar with chip manufacturing knows that the tape-out stage is essential for ensuring the successful launch of a product. The correctness and stability of the I/O (Input/Output) interfaces are directly related to the overall performance and reliability of the chip. How can we ensure the I/O status during the tape-out phase? Let’s take a … Read more
Before an IC chip enters the tape-out phase, engineers must prepare extensively to ensure the smooth progress of subsequent stages, and a reasonable layout design is key to ensuring chip performance, reliability, and cost-effectiveness. 1. Pin Layout Optimization Clearly define the direction and position of the pins, especially keeping the clock pins and analog signal … Read more
Included in the collection #Li Chengguang61 #Tape-Out1 The chip industry is no stranger to tape-out. Tape-out refers to the process of manufacturing chips through a series of steps like an assembly line. This stage is a crucial link between chip design and mass production. In simple terms, it means handing over the designed scheme to … Read more
First, let’s explain what tape-out is; it is not the same as mass production. Tape-out, in English, is called Tape Out, is the process of converting a designed integrated circuit (IC) layout into an actual physical chip. It is like an assembly line, manufacturing chips through a series of process steps. Chip design companies hand … Read more
Click the image at the end of the article to download the report Core Content The report shows that the chip design industry sample covers the entire upstream and downstream supply chain, with the highest proportion of upstream companies (4,762), while the number of midstream manufacturing companies is smaller but has a significant salary sample … Read more
This year’s IIC Shanghai, while similar in arrangement to previous years with forums on power supply, MCU, EDA/IP, and the China IC Leaders Summit, has a notable difference: everyone is talking about AI. Almost all topics revolve around AI—even discussions related to power supply and testing are intertwined with AI. This is closely related to … Read more
Process Node Process Type Technical Features 2nm Logic, Nanosheet (0.75V, shrink) Utilizes nanosheet technology with a 0.75V operating voltage and shrink characteristics, which helps improve chip integration and performance. 3nm Logic, Fin FET (0.75/1.2V, shrink)Logic, Fin FET (0.75/1.2V, Non-shrink) Based on Fin Field Effect Transistor technology, it offers different voltage combinations (0.75/1.2V) with both shrink … Read more
The public account has adjusted the article push rules. Click the blue text above👆to follow and set a star mark, to receive the latest article updates in a timely manner. March 30 (Sunday) Weekend Discussion. RISC-V Chip Concept Catalytic Events: Recently, Academician Ni Guangnan of the Chinese Academy of Engineering stated at the 2025 Xuantie … Read more
Hello everyone, I am Engineer Wang. Today, let’s learn about a company, named: Rockchip Electronics Co., Ltd. (“Rockchip”, stock code: 603893). The reason for introducing this company is that their chips are widely used, and in the embedded field, there are very few hardware engineers who are unaware of them. 011 Introduction Our daily routine … Read more
Recently, while chatting with a prominent figure in the industry, we discussed the topic of chip tape-out failures. I found this to be quite an interesting subject, so I gathered some reasons for chip tape-out failures online and would like to share them here. 1. Incorrect version of the design was used. This issue is … Read more