Now let’s get into today’s main topic (the author is using the battleship STM32 library function version): today I will discuss two knowledge points with you: 1. Analysis of the RTC clock block diagram (important) 2. How time is displayed (brief analysis) 1. Analysis of the RTC Clock Block Diagram (Important) First, let’s familiarize ourselves … Read more
This morning, Huawei HiSilicon officially released the Kirin 950, with detailed performance introduced later in the article. This article also takes the opportunity to review the development process of HiSilicon and how the Kirin 950 was forged. Interested friends can join the discussion. HiSilicon Semiconductor Co., Ltd. is a wholly-owned subsidiary of Huawei and ranks … Read more
The report from Electronic Enthusiasts (by Electronic Enthusiasts) states that 38 years ago, an innovative RISC ISA was born at Stanford University in the United States, leading to the emergence of MIPS. With this project, several founders established MIPS Corporation, which successively launched the R2000 and R3000 microprocessors in the 1980s. Because of this, MIPS … Read more
Overview This article describes the virtualization support of Armv8-A AArch64, including stage 2 page table translations, virtual exceptions, and traps. It introduces some basic hardware-assisted virtualization theories and examples of how some Hypervisors utilize these virtualization features. This text will not discuss how a specific Hypervisor software operates or how to develop a Hypervisor. By … Read more
Related Reading: Differences Between X86 Architecture and Arm Architecture 0. ARMv8 Architecture 1) Basic Concepts of ARMv8 (1) Execution State: The environment in which the processor operates, including register width, supported instruction set, exception model, memory management, and programming model. The ARMv8 architecture defines two execution states: AArch64: 64-bit execution state Provides 31 general-purpose registers … Read more
Background Read the fucking source code! –By Lu Xun A picture is worth a thousand words. –By Gorky Note: Kernel Version: 4.14 ARM64 Processor, Cortex-A53, Dual-core Tools Used: Source Insight 3.5, Visio 1. Introduction To understand Linux page table mapping well, it is necessary to be familiar with the MMU mechanism, so these two modules … Read more
Security in ARMv8-A Systems A secure or trusted operating system protects sensitive information within the system, such as passwords and credit card authentication information stored by users, from attacks. Security is defined by the following principles: Confidentiality: Protects sensitive information on the device from unauthorized access. This can be achieved through various methods, such as … Read more
Click the blue "Arm Selected" in the top left corner and select "Set as Favorite" Table of Contents 1. Why Use Cache? 2. Background: Changes in Architecture? 3. Cache Hierarchy – Big.LITTLE Architecture (Example: A53) 4. Cache Hierarchy – DynamIQ Architecture (Example: A76) 5. What Are the Sizes of L1/L2/L3 Cache? 6. Introduction to Cache-Related … Read more
Click the blue "Arm Selected" in the top left corner and select "Set as Star" Environment: Linux kernel 4.4, (SCR.IRQ=0, SCR.FIQ=1) OP-TEE 3.6 (SCR.IRQ=0, SCR.FIQ=0) ARMV8GICV3 When the CPU is in the secure side and a non-secure interrupt arrives, depending on SCR.NS=0 / the interrupt in the non-secure group 1 group, the CPU interface will … Read more
Click the blue 'Arm Selection' at the top left and select 'Mark as Favorite' 1. Concepts of Exceptions and Interrupts AArch64 exception and interrupt handling In the AArch64 architecture, exceptions and interrupts are one of the key mechanisms to ensure the normal operation of the system. An exception refers to a situation where the system … Read more