Everyone in the electronics industry knows a lot about chips and various packages, but do you know how a chip is designed? Do you know how the designed chip is manufactured? After reading this article, you will have a general understanding.
The chip manufacturing process is like building a house with Lego blocks. First, there is the wafer as the foundation, and then layers are stacked up in the chip manufacturing process to produce the necessary IC chips (which will be introduced later). However, without a design blueprint, even the strongest manufacturing capabilities are useless, hence the role of the architect is crucial. But who is the architect in IC design? This article will introduce IC design.
In the IC production process, ICs are mainly planned and designed by specialized IC design companies. Renowned companies like MediaTek, Qualcomm, and Intel design their own IC chips, providing various specifications and performance options for downstream manufacturers to choose from. Because ICs are designed by various companies, IC design heavily relies on the skills of engineers, and the quality of engineers affects the value of a company. However, what steps do engineers follow when designing an IC chip? The design process can be simply divided as follows.
Step One: Set Goals
In IC design, the most important step is specification formulation. This step is like deciding how many rooms and bathrooms to have before designing a building, and what building regulations need to be adhered to. After determining all functions, the design can proceed without wasting extra time on subsequent modifications. IC design also needs to go through similar steps to ensure that the designed chip has no errors.
The first step in specification formulation is to determine the purpose and performance of the IC, setting the overall direction. Next, it is necessary to check what agreements need to be complied with. For example, a wireless network card chip must comply with IEEE 802.11 standards; otherwise, the chip will not be compatible with market products, preventing it from connecting with other devices. Finally, the implementation method of the IC is established, with different functions assigned to different units and methods of connecting different units determined, thus completing the specification formulation.
After completing the specifications, the next step is to design the details of the chip. This step is like sketching out the preliminary design of a building, outlining the overall profile for subsequent drafting. In IC chips, hardware description languages (HDL) are used to describe the circuits. Commonly used HDLs include Verilog and VHDL, which can easily express the functions of an IC through code. Next, the correctness of the program functionality is checked and continuously modified until it meets the expected functions.
▲ Example of a 32-bit adder in Verilog.
With Computers, Everything Becomes Easier
With a complete plan, the next step is to draw the flat design blueprint. In IC design, the logic synthesis step involves placing the verified HDL code into electronic design automation tools (EDA tools), allowing the computer to convert the HDL code into logical circuits, producing circuit diagrams like the following. After that, repeatedly confirm whether this logic gate design meets specifications and modify it until the functionality is correct.
▲ Result after synthesizing the control unit.
Finally, the synthesized code is placed into another set of EDA tools for circuit layout and routing (Place And Route). After continuous testing, the following circuit diagram is formed. In the diagram, different colors such as blue, red, green, and yellow represent different masks. As for how to use these masks?
▲ Commonly used calculation chip – FFT chip, result after circuit layout and routing.
Layered Masks, Stacking a Chip
First of all, it is known that an IC will produce multiple masks, with each layer having its own tasks. The following image is a simple example of a mask, using CMOS, the most basic component in integrated circuits. CMOS stands for Complementary Metal-Oxide-Semiconductor, which combines NMOS and PMOS to form CMOS. As for what metal-oxide-semiconductor (MOS) is, this widely used component in chips is difficult to explain, and it may be hard for the general reader to understand, so we will not delve into it further here.
In the diagram, the left side shows the circuit diagram formed after circuit layout and routing. It has been established that each color represents a mask. The right side shows how each mask is laid out. The manufacturing process starts from the bottom layer, following the method described in the previous IC chip manufacturing, layer by layer, until the desired chip is produced.
At this point, there should be a preliminary understanding of IC design. Overall, IC design is a very complex profession, and thanks to the maturity of computer-aided software, IC design can be accelerated. IC design companies heavily rely on the intelligence of engineers, and each step described here has its specialized knowledge, which could independently form multiple specialized courses, such as writing hardware description languages, which not only requires familiarity with programming languages but also an understanding of how logic circuits operate, how to convert required algorithms into programs, and how synthesis software converts programs into logic gates.
In semiconductor news, there are always mentions of wafer fabs indicated by sizes such as 8-inch or 12-inch wafers. However, what exactly is a wafer? What does the 8-inch refer to? What difficulties are there in producing large-size wafers? The following will introduce the most important foundation of semiconductors – “what a wafer is”.
A wafer is the foundation for manufacturing various computer chips. We can compare chip manufacturing to building a house with Lego blocks, stacking layer upon layer to achieve the desired shape (that is, various chips). However, without a good foundation, the house will be crooked and not as desired. To create a perfect house, a stable substrate is needed. For chip manufacturing, this substrate is the wafer described next.
(Source: Flickr/Jonathan Stewart CC BY 2.0)
First, recall the small circular protrusions on the surface of Lego blocks when playing with them as a child. With this structure, we can securely stack two blocks together without glue. Chip manufacturing also uses a similar method to secure the atoms and substrate added later. Therefore, we need to find a substrate with a smooth surface to meet the conditions required for subsequent manufacturing.
In solid materials, there is a special crystal structure – monocrystalline. It has the characteristic of tightly packed atoms, forming a flat atomic surface. Therefore, using monocrystalline to make wafers can meet the above requirements. However, how to produce such materials involves two main steps: purification and crystal pulling, after which such materials can be completed.
How to Manufacture Monocrystalline Wafers
Purification is divided into two stages. The first step is metallurgical-grade purification, in which carbon is added to reduce silicon dioxide to silicon with a purity of over 98%. Most metal refining, such as iron or copper, is done this way to obtain sufficiently pure metals. However, 98% is still not enough for chip manufacturing, so further purification is needed. Thus, the Siemens process is used for purification, obtaining the high-purity polysilicon required for semiconductor processes.
▲ Silicon pillar manufacturing process (Source: Wikipedia)
Next is the crystal pulling step. First, the high-purity polysilicon obtained earlier is melted to form liquid silicon. Then, a seed of single-crystal silicon is placed in contact with the liquid surface, and while rotating, it is slowly pulled upward. The reason for needing a single-crystal silicon seed is that the arrangement of silicon atoms is similar to people lining up; a leader is needed to guide how later atoms should be arranged. The silicon seed acts as that leader, guiding the subsequent atoms on how to line up. Finally, once the silicon atoms solidify after leaving the liquid surface, a neatly arranged single-crystal silicon pillar is completed.
▲ Single-crystal silicon pillar (Source: Wikipedia)
So, what do the 8-inch and 12-inch represent? They refer to the diameter of the silicon wafers produced after processing the silicon pillars, which look like the body of a pencil. As for the difficulties of manufacturing large-size wafers, as mentioned earlier, the production process of silicon pillars is similar to making cotton candy; it is quite challenging to produce large and solid cotton candy. The pulling process also requires precise control of speed and temperature, which affects the quality of the pillars. Therefore, as the size increases, the requirements for speed and temperature in the pulling process become higher, making it more difficult to produce high-quality 12-inch wafers compared to 8-inch wafers.
However, a whole silicon pillar cannot be used directly as a substrate for chip manufacturing. To produce thin silicon wafers, the silicon pillar must be sliced horizontally with a diamond knife, and the slices are then polished to form silicon wafers required for chip manufacturing. After so many steps, the manufacturing of the chip substrate is successfully completed, and the next step is to stack the house, which is the chip manufacturing process. How to make chips?
After introducing what silicon wafers are, we also know that manufacturing IC chips is like building a house with Lego blocks, stacking layer upon layer to create the desired shape. However, building a house involves many steps, and IC manufacturing is no different. What steps are involved in IC manufacturing? This article will introduce the process of IC chip manufacturing.
Before we begin, we need to understand what IC chips are. IC, short for Integrated Circuit, indicates that it combines designed circuits stacked together. By this method, we can reduce the area required for connecting circuits. The following image shows a 3D diagram of an IC circuit; from the image, it is clear that its structure resembles the beams and columns of a building, stacked layer by layer, which is why IC manufacturing is compared to building a house.
▲ 3D cross-section of an IC chip. (Source: Wikipedia)
From the above 3D cross-section of the IC chip, the deep blue part at the bottom is the wafer introduced in the previous section, making it clearer how important the wafer substrate is in the chip. The red and earth-yellow parts are the areas to be completed during IC manufacturing.
First, the red part can be likened to the lobby of a high-rise building. The lobby is the entrance of a building, where all traffic flows through, and it usually has more functionalities than other floors. Therefore, compared to other floors, it is more complex to construct and requires more steps. In the IC circuit, this lobby is the logic gate layer, which is the most crucial part of the entire IC. By combining various logic gates, a fully functional IC chip is achieved.
The yellow parts represent the general floors. Compared to the first floor, they do not have overly complex structures, and there are not many changes during construction. The purpose of this layer is to connect the logic gates of the red part. The reason for needing so many layers is that there are too many lines to connect. When a single layer cannot accommodate all the lines, multiple layers must be stacked to achieve this goal. In this process, lines from different layers will connect up and down to meet the wiring requirements.
Layered Construction, Building Up Layer by Layer
After understanding the structure of the IC, the next step is to introduce how to manufacture it. Imagine if you want to create intricate designs using a spray paint can, you need to first cut out a stencil and place it on the paper. Then, spray the paint evenly over the paper, and once the paint dries, remove the stencil. By continuously repeating this process, you can complete a neat and complex design. IC manufacturing is done in a similar manner, stacking layer by layer using masking methods.
IC manufacturing can be simply divided into the four steps above. Although the actual manufacturing process may vary, and the materials used differ, they generally adopt similar principles. This process is somewhat different from painting; IC manufacturing involves applying paint first and then masking, while painting involves masking before painting. The following introduces each process.
Metal Sputtering: Uniformly sprinkle the desired metal material onto the wafer to form a thin film.
Photoresist Coating: First, place the photoresist material on the wafer, and through a mask (the principle of the mask will be explained next time), expose the unwanted parts to light, destroying the structure of the photoresist material. Next, use a chemical agent to wash away the destroyed material.
Etching Technology: Etch the silicon wafer that is not protected by the photoresist using an ion beam.
Photoresist Removal: Use a photoresist remover to dissolve the remaining photoresist, thus completing one cycle of the process.
In the end, many IC chips will be completed on a single wafer. After that, the completed square IC chips can be cut out and sent to packaging factories for packaging. As for what packaging factories are, that will be explained later.
▲ Comparison of wafers of various sizes. (Source: Wikipedia)
Samsung and TSMC are fiercely competing in advanced semiconductor processes, each trying to seize the initiative in wafer foundry to secure orders, almost turning into a battle of 14nm versus 16nm. However, what do the numbers 14nm and 16nm really mean, and which part do they refer to? What benefits and challenges will arise from shrinking the process? The following will provide a brief explanation of the nanometer process.
How Small is a Nanometer?
Before we begin, it is essential to understand what a nanometer is. Mathematically, a nanometer is 0.000000001 meters, but this is a rather poor example, as we only see many zeros after the decimal point without a tangible feeling. If we compare it to the thickness of a fingernail, it might be more apparent.
Measuring with a ruler shows that the thickness of a fingernail is about 0.0001 meters (0.1 mm), meaning if you try to cut a fingernail’s side into 100,000 lines, each line would be approximately equal to 1 nanometer. This gives a rough idea of how tiny a nanometer is.
Understanding how small a nanometer is, we also need to grasp the purpose of shrinking the process. The primary goal of shrinking transistors is to pack more transistors into smaller chips, preventing chips from growing larger as technology improves. Additionally, it can increase the processing efficiency of processors, reduce size to lower power consumption, and make it easier to fit smaller chips into portable devices, meeting future demands for thinness and lightness.
Returning to the nanometer process, for example, a 14nm process refers to the minimum feature size that can be achieved in the chip, meaning that the smallest line can be as small as 14nm. The following image shows the appearance of traditional transistors, serving as an example. The main purpose of shrinking transistors is to reduce power consumption, but which part should be shrunk to achieve this? The “L” in the lower left image indicates the part we aim to reduce. By shortening the gate length, the current can take a shorter path from the drain to the source (if interested, you can search for MOSFET on Google for a more detailed explanation).
(Source: www.slideshare.net)
Furthermore, computers operate using 0s and 1s. How can transistors fulfill this purpose? The method is to determine whether an electric current flows through the transistor. When voltage is supplied at the gate (the green square), current will flow from the drain to the source; if no voltage is supplied, the current will not flow, thus representing 1 and 0. (If interested, you can look up Boolean algebra to understand why we use 0 and 1 for judgment, as this method is used to construct computers.)
Physical Limitations of Size Reduction
However, the process cannot be shrunk indefinitely. When transistors are shrunk to around 20nm, quantum physical issues arise, causing leakage currents that negate the benefits gained from reducing “L”. To improve this, the concept of FinFET (Tri-Gate) is introduced, as shown in the upper right image. In explanations previously provided by Intel, it is known that by adopting this technology, leakage currents caused by physical phenomena can be reduced.
（Source: www.slideshare.net）
More importantly, this method can increase the contact area between the gate and the lower layer. In traditional methods (the left image), the contact surface is only a flat plane. However, by using FinFET (Tri-Gate) technology, the contact surface becomes three-dimensional, easily increasing the contact area, thus helping to reduce size while maintaining the same contact area.
Finally, why do many say that major manufacturers face significant challenges when entering the 10nm process? The main reason is that one atom is about 0.1 nanometers in size. At 10nm, a line consists of less than 100 atoms. This makes manufacturing exceedingly difficult, and even a single atomic defect, such as an atom falling out during production or impurities, can lead to unknown phenomena, affecting product yield.
If you can’t imagine this difficulty, you can conduct a small experiment. Arrange 100 small beads into a 10×10 square on the table, then cut a piece of paper to cover the beads and use a small brush to brush away the surrounding beads, finally forming a 10×5 rectangle. This will help you understand the challenges faced by major manufacturers and how arduous it is to achieve this goal.
As Samsung and TSMC have recently completed mass production of 14nm and 16nm FinFET, both are vying for the next generation of Apple’s iPhone chip foundry. We will witness exciting commercial competition while also benefiting from more power-efficient and thinner phones, thanks to the advantages brought by Moore’s Law.
After a lengthy process from design to manufacturing, an IC chip is finally obtained. However, a chip is quite small and thin, and without external protection, it can be easily scratched or damaged. Furthermore, due to the chip’s tiny size, it is challenging to manually place it on a circuit board without a larger-sized casing. Therefore, the following will describe packaging.
Currently, there are two common types of packaging: one is the DIP package, often seen in electric toys, which looks like a black centipede, and the other is the BGA package, commonly seen when purchasing boxed CPUs. Other packaging methods include PGA (Pin Grid Array) used in early CPUs or QFP (Quad Flat Package), an improved version of DIP. Due to the numerous types of packaging methods, we will introduce DIP and BGA packaging.
Traditional Packaging, Timeless
First, we introduce the Dual Inline Package (DIP). From the following image, we can see that IC chips using this packaging appear like a black centipede under double rows of pins, making a lasting impression. This packaging method is the earliest adopted IC packaging technology, known for its low cost, suitable for small chips that do not require many connections. However, since they are mostly made of plastic, they have poor heat dissipation and cannot meet the requirements of current high-speed chips. Therefore, those using this packaging are mostly enduring chips, such as the OP741 in the image below, or smaller IC chips with fewer connection holes that do not require high operational speeds.
▲ The IC chip on the left is OP741, a common voltage amplifier. The right image is its cross-section, where the chip is connected to the metal leads using gold wire. (Source: Left image Wikipedia, Right image Wikipedia)
As for the Ball Grid Array (BGA) packaging, it is smaller in volume compared to DIP, making it easy to fit into smaller devices. Additionally, since the pins are located underneath the chip, BGA can accommodate more metal pins compared to DIP, making it suitable for chips that require more connections. However, this packaging method is more expensive and complex in terms of connections, so it is mostly used in high-priced products.
▲ The left image shows a chip using BGA packaging. The right image is a schematic diagram of BGA packaging using flip chip technology. (Source: Left image Wikipedia) The rise of mobile devices has brought new technologies to the stage.
However, using the above packaging methods consumes a considerable amount of space. Nowadays, mobile devices and wearable devices require many components, and if each component is independently packaged, it will take up a vast amount of space. Therefore, there are currently two methods to meet the demand for reduced size: SoC (System On Chip) and SiP (System In Package).
When smartphones first emerged, the term SoC could be found in many financial magazines. But what exactly is SoC? In simple terms, it integrates different functional ICs into a single chip. This method not only reduces the size but also minimizes the distance between different ICs, improving the speed of the chip. The manufacturing method involves placing various ICs together during the IC design phase and then using the design process previously introduced to create a mask.
However, SoC is not without its drawbacks. Designing an SoC requires a considerable amount of technical collaboration. When IC chips are packaged separately, each has external protection, and the distance between ICs is relatively far apart, reducing the likelihood of interference. However, when all ICs are packaged together, it becomes a nightmare. IC design companies must shift from simply designing ICs to understanding and integrating various functional ICs, increasing the workload for engineers. Additionally, many situations arise, such as high-frequency signals from communication chips potentially interfering with other functional ICs.
Moreover, SoC needs to obtain IP (intellectual property) licenses from other manufacturers to incorporate pre-designed components into the SoC. This requires obtaining the design details of the entire IC to create a complete mask, which simultaneously increases the design costs of SoC. Some may question why not design one from scratch? Because designing various ICs requires a vast amount of knowledge related to that IC, only wealthy companies like Apple can afford to hire top engineers from various well-known companies to design an entirely new IC. Collaborating and licensing is still more cost-effective than developing it independently.
Compromise Solution: SiP Emerges
As an alternative, SiP has taken the stage of integrated chips. Unlike SoC, it involves purchasing ICs from various manufacturers and packaging them together at the final stage, thus eliminating the need for IP licensing, significantly reducing design costs. Additionally, since they are independent ICs, the degree of interference between them is greatly reduced.
▲ The Apple Watch adopts SiP technology to package the entire computer architecture into a single chip, not only meeting the expected performance but also reducing size, allowing more space for batteries in the watch. (Source: Apple official website)
After packaging is completed, the next stage is testing, where it is confirmed whether the packaged IC operates normally. Once verified, it can be shipped to assembly plants to become the electronic products we see. At this point, the semiconductor industry has completed the entire production task.
Source: Wu Zhengdao TechNews
