When debugging or programming an MCU, data is first encapsulated into USB data packets. Then, the PC sends these data packets to the bridge via the USB interface. The bridge decomposes the USB data packets into UART data, and the UART data arrives asynchronously to the MCU, and is processed according to the application. However, note that USB is typically much faster than UART, requiring a FIFO buffer to compensate for the difference and avoid data loss. Thus, the bridge must be correctly configured with the baud rate to meet the communication needs of the MCU.
The MCU can also send data back to the PC through the same USB/UART bridge, responding to the PC. The bridge will convert these UART data back into USB data packets and then transmit them to the PC. The conversion between USB and UART may introduce timing or flow errors. Components like FTDI or CP210x have built-in error handling mechanisms to ensure reliable communication. The specific communication process is as follows:
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Jingxin SoC Design Video + Document + Practice + One-on-One Lifetime Guidance (Free Video, No Time Limit)
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Jingxin SoC Verification Video + Document + Practice + One-on-One Lifetime Guidance (Free VideoNo Time Limit)
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Jingxin SoC Mid-End Video + Document + Practice + One-on-One Lifetime Guidance (Free VideoNo Time Limit)
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Jingxin SoC Backend Video + Document + Practice + One-on-One Lifetime Guidance (Free VideoNo Time Limit)
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12nm 2.5GHz A72 Low Power DVFS Practical Training (Price is less than half of the industry average)
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DDR4/3 Project Practical Training (Price is less than half of the industry average)
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Providing SoC, MCU, ISP, CIS and other chip design, verification, DFT design services
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Providing DDR/PCIE/MIPI/CAN/USB/ETH/QSPI/UART/I2C and other IP designs
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Providing backend design for 7nm, 12nm, 28nm, 40nm, 55nm, 65nm, 90nm
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Providing customized chip design services and design training for universities and enterprises
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High-speed interface Verilog design implementation -
From image algorithms to RTL design implementation -
MIPI, ISP’s Verilog implementation and simulation -
Lint, CDC checks and UVM verification -
SoC subsystem C driver simulation -
Post-simulation -
SoC subsystem-level UVM environment setup -
SoC subsystem-level UVC environment setup -
SoC subsystem-level VIP environment setup -
SoC subsystem DMA SRAM UVM joint verification -
SoC subsystem UART UVC verification -
SoC subsystem long packet, short packet, super long packet, glitch packet, packet header/footer error UVM verification -
DFT design (chip-level) -
Synthesis logic synthesis (chip-level) -
Low-power UPF design, CLP technology -
formal verification and other techniques
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Low-power design
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Layout and routing (low-power FF flow) -
StarRC/QRC -
STA/Tempus -
Power analysis -
DRC/LVS design -
dpc – Bad pixel correction
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blc – Black level correction
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bnr – Bayer noise reduction
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dgain – Digital gain
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demosaic – Demosaicing
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wb – White balance gain
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ccm – Color correction matrix
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csc – Color space conversion (RGB2YUV conversion formula based on integer optimization)
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gamma – Gamma correction (brightness-based table lookup Gamma correction)
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ee – Edge enhancement
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stat_ae – Auto exposure statistics
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stat_awb – Auto white balance statistics
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Lint check, frontend simulation,
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Complete mid-end and backend flow,
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Complete clp check, complete post-simulation
Jingxin SoC v4.0 Chip Full Process Practical Training
Lifetime guidance and one-on-one coaching are the features of Jingxin SoC Training Camp!
Hand-in-hand teaching you to build the SoC from beginner to advanced, leading you to master architecture, algorithms, design, verification, DFT, and the full low-power backend process! Live videos are upgraded irregularly! Let you quickly surpass your peers!
Jingxin Full Process Courses are as follows:
Jingxin Advanced Courses:
Course Registration WeChat:
At the same time, I shared some full process knowledge of chips in the Knowledge Planet, including design, verification, DFT, backend full process knowledge, and a large number of technical documents. If you, like me, crave knowledge and progress, you are welcome to join the discussion and learning, and make progress together!
Jingxin’s main business is design service + one-on-one chip guidance training!
In addition, the editorial team provides chip Design Service, including:
In addition, Jingxin’s entrepreneurial version SoC Cortex-A processor + NOC + BootROM has successfully booted. Currently, MIPI has already smoked, but the MIPI2DDR module is still under development. There is not enough energy, and students who are interested can join the development, converting MIPI CSI idi/ipi to AXI to DDR, with priority given to the experienced.
Hand-in-hand teaching you to master SoC algorithms, design, verification, DFT, backend full process low power!
Jingxin SoCv3.0 is a low-power multimedia SoC used for full process practical training of chips!
Jingxin SoC system is divided into three levels of power management and integrates low-power RISC-V processors, ITCM SRAM, DTCM SRAM, integrates MIPI, ISP, USB, QSPI, UART, I2C, GPIO and other IPs, using SMIC40 process for chip production.
Just the content of one verification course is equivalent to 3-4 courses from other training institutions, and the price is only 1/6 of theirs
(4) In the SoC backend course, you will learn
Just the content of one backend course is equivalent to 3-4 courses from other training institutions, and the price is only 1/6 of theirs
The course provides servers for everyone to practice! Taking you from algorithms, frontend, DFT to backend to participate in SoC project design. Please contact the host for registration! Contact WeChat: 135-4139-0811
The data path for image processing in Jingxin SoC training camp:
Jingxin SoC’s CRG design:
One-click completion of C code compilation, simulation, synthesis, DFT insertion, formal verification, layout and routing, parasitic parameter extraction, STA analysis, DRC/LVS, post-simulation, formal verification, power analysis, and other full processes. The upgraded chip design engineering V4.0 flow is as follows:
SoC One-Click Execution Flow
MIPI DPHY+CSI2 Decoding
Classic design in digital circuits: Implementation of multiple communication data lane merging
Classic design in digital circuits: Implementation of multiple communication data lane distribution
Jingxin SoC Verification Architecture
Jingxin SoC full-chip verification architecture:
Jingxin’s senior students told me that a master’s degree studying abroad in country X at a foreign chip giant has a salary of over 200,000+ USD! Converted to RMB is over 1 40 million, just a 25-year-old young man! Salary over 1.4 million!
I went to check the salary on Glassdoor:
1-3 years experience of ASIC Engineer salary quoted at 212K USD, 200K USD.
7-9 years of experience in ASIC Engineer salary quoted at 311K USD, 300K USD.
Of course, specific salaries also depend on each candidate’s level and job matching.
Education, project experience are very important, looking forward to more good news from Jingxin comrades! Going abroad, the world is more exciting! The positive energy of the Jingxin SoC project is so great that I am shocked myself. I will continue to polish it and let Jingxin comrades succeed together!
Jingxin SoC UPF Low Power Design
Full chip UPF low power design (including DFT design)
Before low power design, the power consumption was 27.9mW.
After low power design, the power consumption was 0.285mW, a reduction of 98.9%!
Voltage drop check:
Low power check:
Chip layout design V1.0
Chip layout design V2.0
Chip layout design V4.0
The DRC/LVS of low power design, the LVS practice of the chip top layer is of great value and challenging! Unique experience sharing in the industry.
ISP Image Processing
CNN Image Recognition
Supports handwritten digit AI recognition:
Simulation results: Simulated recognition of the above images 7, 2, 1, 0, 4, 1, 4, 9
Jingxin SoC 3.0 ISP:
Jingxin SoC V3.0 DFT scheme:
If you, like me, crave progress and want to master the full process of chip design, welcome to join my Knowledge Planet, grow wildly, and progress together! Become a chip boss as soon as possible!
Thank you very much to the Jingxin students for your recognition, trust, and support for Jingxin. Your encouragement makes me very grateful. I will definitely work harder to refine Jingxin SoC practical courses. I promise to achieve zero negative reviews, allowing everyone, whether experienced or inexperienced, to grow from the Jingxin training camp!
Recently, students have been asking me about offer choices. Seeing everyone getting their desired offers after improving through Jingxin training makes me very happy, congratulations to everyone for getting their desired offers!
In addition, a Jingxin VIP student of mine, a master’s degree from a 985 university in Chengdu with 7 years of experience, previously improved through Jingxin training and got his desired offer. I am envious of these three offers! Last time I initiated a vote, and today I will announce the results. Let’s first look at the three offer situations:
1. A certain GPU company, monthly salary 58,000, year-end 4 months totaling 232,000, annual salary 928,000, position is SoC frontend design, provident fund 12%;
2. Multimedia SOC manufacturer JC, monthly salary 65,000, year-end bonus 2 months totaling 130,000, annual salary 910,000, position is SoC chip design engineer, provident fund 12%;
3. State-owned enterprise X Microelectronics, monthly salary 55,000, year-end bonus 4 months totaling 220,000, annual salary 880,000, serving as a digital IC design engineer, mainly engaged in SOC chip design, provident fund 10%
Here I supplement the announcement of the last voting results:
From the results, it can be seen that the market is not good, and everyone is looking at the stability of state-owned enterprises and military industries. GPU is still the technical choice. Although GPU companies are competing fiercely, there is still a prospect, but IPC SOC has the lowest votes, and the internal competition has not brought a significant increase in the market.
In addition, a senior student from Jingxin told me that a master’s degree studying abroad in country X at a foreign chip giant has a salary of over 200,000+ USD! Converted to RMB is over 1 40 million, just a 25-year-old young man! Salary over 1.4 million! Keep learning technology, young man.
If you, like me, crave progress and want to master the full process of chip design, welcome to join my Knowledge Planet, grow wildly, and progress together!
Jingxin SoC V3.0 course provides servers for everyone to practice! Hand-in-hand teaching you to learn SoC’s algorithms, frontend, DFT, and backend full process practical training.
Course Registration WeChat:
Rich tutorial documents
Students in Jingxin Training Camp asked how to add PAD to IO? Please think about how to achieve the best IO and PAD for Jingxin SoC?
VIP students in the SoC training camp asked why the low power cell was not inserted into the netlist?
Although asking questions is encouraged, when we encounter problems, we should first think proactively and solve the problems ourselves. If we really can’t solve it, we can ask for help, so we can grow faster.
First, I got this question and opened the log. Checking the log is a virtue in IC design! I found that after the EDA tool read the UPF file, it reported the following warning, using many ff libraries.
The above error indicates that the UPF specified the voltage as 0.99V, while the CELL is 1.20V. The voltage mismatch caused the logical synthesis netlist not to insert the MV CELL. Note that when synthesizing, we used the ss library, how could it be the ff library? Opening the constraint script found the following bug:
So, change the constraint from ff to ss. Run again, and the result will come out:
In the low power design section, I will leave a small bug in the design, which is very simple. I will not disclose the answer; everyone must think more and run more, so that they can learn deeply.
Training students please note that Jingxin SoC uses the always-on power domain’s pwrdown_mux signal as the switch control signal for the power switch cell. However, there is a small issue in the design that is not exactly a bug, but for the UPF low power flow, it is undoubtedly a bug!
Training students please log in to the server to track the pwrdown signal, paying attention to its load conditions. The RTL code is as follows:
Combining the PR output netlist, we can do a clp low power check. The script can be found on the server. It can be found that the clp reports that the switch control signal of the power switch cannot be found.
It must be said how important clp checks are for low power, and how important they are for chip design! The value of Jingxin SoC lies in connecting all these small knowledge points of the chip design full process! What are you hesitating about? Hurry up and register to join!
In the mid-process of chip design, Jingxin SoC will insert isolation cells into the UPF constraints, but cannot insert power switch cells, so the control signal pwrdown_mux of the power switch cell will be optimized away without load (optimized away). Therefore, it is necessary to set the above MUX device as dont_touch or make pwrdown_mux a module port and prohibit auto_ungroup (and set no_boundary_optimization), so that this signal can be preserved for the backend to control the power switch. Please complete the code modification based on the complete flow environment and complete the following tasks:
Students in Jingxin Training Camp asked why the same floorplan runs quickly for some students while others encounter a lot of DRC issues (EDA tools keep iterating), making it impossible for the tool to complete. What specific problem is this?
First, I found that the student’s stripe defined TM2 as horizontal, while those familiar with Jingxin’s process know that the preference direction of TM2 is VERTICAL.
Checking Jingxin’s lef library file can also confirm:
How much impact does using the wrong direction have? Everyone should practice on Jingxin SoC’s backend flow to find out; practice makes perfect.
Students in Jingxin Training Camp asked why the PR took a whole day and night (24 hours) to complete the routing but still had a lot of DRC errors? I have minimized the design scale to speed up PR design; in fact, it should take 2 hours to complete routing. Why is it so slow? The reason is the routing of low-power cells. Specific reasons and solutions welcome to join the Jingxin training camp for discussion.
The errors are mainly concentrated on M4. Please think about how to solve them.
Students in Jingxin Training Camp asked why the second PG pin (VDDG) of the power switch cell is connected from M1, not M2. What problems might arise? How to solve it?
Students in Jingxin Training Camp asked why the Corner Pad LVS is not passing. How to handle it?
After completing the frontend design simulation and DFT of Jingxin SoC training, we come to the backend flow. This tutorial teaches you how to run the digital backend flow in one click.
The script command is as follows:
tclsh ./SCRIPTS/gen_flow.tcl -m flat all
Before generating the flow script, you need to configure setup.tcl and other related parameters. Please refer to the [only one on the entire network] [full-stack chip engineer] providing self-developed Jingxin SoC frontend engineering, DFT engineering, backend engineering, taking you from algorithms, frontend, DFT to backend to participate in SoC project design.
Students in Jingxin SoC training camp asked why Innovus reported an error when reading the completed floorplan def file? First, check the log:
Reading floorplan file – ./data_in/DIGITAL_TOP.def (mem = 1595.0M).
#% Begin Load floorplan data … (date=10/23 22:38:01, mem=1579.3M)
**ERROR: (IMPFP-710): File version unknown is too old.
In the past EDI period, we could load the floorplan by defining fp_file:
set vars(fp_file) “./data_in/DIGITAL_TOP.def”
However, now Innovus has upgraded and abandoned the fp_file loading method. Of course, you can use the old version of EDI9.1 and earlier to add fp_file, then save it as a new version, but this method is obviously unnecessary. Just like the log prompt said, checking the log is a very good engineering habit.
The input floorplan file is too old and is not supported in EDI 10.1 and newer.
You can use EDI 9.1 and before to read it in, then save again to create a new version.
My intuition tells me to check which def version the student saved?
The student’s saving method is as follows:
So how to solve it? Please join the Jingxin training camp for practice.
Jingxin SoC uses many asynchronous FIFOs. Students interested in asynchronous RTL implementation can extract asynchronous FIFOs to observe the layout connections:
Check the area of all asynchronous FIFO cells;
dbget [dbget top.insts.pstatus unplaced -p].area
Check the names of all asynchronous FIFO cells:
dbget [dbget top.insts.pstatus unplaced -p].name
So how to extract the asynchronous paths to observe the layout routing? How to report timing? More content can be found in the Knowledge Planet and SoC training camp.
This is the content I shared today. If you, like me, crave progress and want to master the full process of chip design, welcome to join my Knowledge Planet, grow wildly, and progress together!
Welcome to join the SoC MCU full process design group, first add me on WeChat, verify your position, and then enter the group!
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