Jingxin SoC v4.0 Chip Full Process Practical Training
Lifetime mentorship and one-on-one guidance are the features of Jingxin SoC training camp!
We will teach you step by step to build SoC, from beginner to advanced, helping you master architecture, algorithms, design, verification, DFT, and backend processes with low power consumption!Live videos are updated irregularly! Let you quickly surpass your peers!
Jingxin Full Process Curriculum is as follows:
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Jingxin SoC Design Video + Documentation + Practical + One-on-One Lifetime Mentorship (Free Video, No Time Limit)
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Jingxin SoC Verification Video + Documentation + Practical + One-on-One Lifetime Mentorship (Free Video No Time Limit)
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Jingxin SoC Mid-level Video + Documentation + Practical + One-on-One Lifetime Mentorship (Free Video No Time Limit)
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Jingxin SoC Backend Video + Documentation + Practical + One-on-One Lifetime Mentorship (Free Video No Time Limit)
Jingxin Advanced Courses:
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12nm 2.5GHz A72 Low Power DVFS Practical Training(Price is less than half of peers)
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DDR4/3 Project Practical Training(Price is less than half of peers)
Course Registration WeChat:
At the same time, I share some full process knowledge about chips in the knowledge star field, including design, verification, DFT, backend full process knowledge, and a large number of technical documents. If you, like me, are eager for knowledge and progress, you are welcome to join the discussion and learning, and make progress together!
Jingxin’s main business is design service + one-on-one chip mentoring training!
Additionally, the editor’s team provides chip Design Service, which includes:
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Providing SoC, MCU, ISP, CIS chip design, verification, DFT design services
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Providing DDR/PCIE/MIPI/CAN/USB/ETH/QSPI/UART/I2C IP design
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Providing backend design for 7nm, 12nm, 28nm, 40nm, 55nm, 65nm, 90nm
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Providing customized chip design services and training for universities and enterprises
In addition, the Jingxin startup version SoC Cortex-A processor + NOC + BootROM has successfully booted. Currently, MIPI has passed initial testing, but the MIPI2DDR module is still halfway through development. Interested students can join the development to convert MIPI CSI idi/ipi to AXI to DDR, with priority given to experienced individuals.
We will teach you step by step to master SoC algorithms, design, verification, DFT, and backend full process low power consumption!
Jingxin SoCv3.0 is a low-power multimedia SoC used for chip full process practical training!
Jingxin SoC system is divided into three levels of power management and integrates a low-power RISC-V processor, ITCM SRAM, DTCM SRAM, and integrates MIPI, ISP, USB, QSPI, UART, I2C, GPIO, and other IPs, using SMIC40 process.
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High-speed interface Verilog design implementation -
From image algorithms to RTL design implementation -
MIPI, ISP Verilog implementation and simulation -
Lint, CDC checks and UVM verification -
SoC subsystem C driver simulation -
Post-simulation
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SoC subsystem-level UVM environment construction -
SoC subsystem-level UVC environment construction -
SoC subsystem-level VIP environment construction -
Joint verification of SoC subsystem’s DMA SRAM UVM -
SoC subsystem’s UART UVC verification -
SoC subsystem’s long packet, short packet, ultra-long packet, glitch packet, header/footer error UVM verification
Just the content of one verification course is equivalent to 3-4 courses from other training institutions, and the price is only 1/6
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DFT design (chip-level) -
Synthesis logic synthesis (chip-level) -
Low power UPF design, CLP technology -
Formal verification and other techniques
(4) In the SoC backend course, you will learn
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Low power design
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Layout and routing (low power FF flow) -
StarRC/QRC -
STA/Tempus -
Power analysis -
DRC/LVS design
Just the content of one backend course is equivalent to 3-4 courses from other training institutions, and the price is only 1/6
The courses provide servers for everyone to practice! Taking you from algorithms, frontend, DFT to backend full process participation in SoC project design. Please contact the host to register! Contact WeChat: 135-4139-0811
The data path for image processing in Jingxin SoC training camp:
Jingxin SoC’s CRG design:
One-click completion of C code compilation, simulation, synthesis, DFT insertion, formal verification, layout and routing, parasitic parameter extraction, STA analysis, DRC/LVS, post-simulation, formal verification, power analysis, and other full processes. The upgraded chip design engineering V4.0 flow is as follows:
SoC One-Click Execution Flow
MIPI DPHY+CSI2 Decoding
Classic designs in digital circuits: Implementation of multiple communication data lane merging designs
Classic designs in digital circuits: Implementation of multiple communication data lane distribution
Jingxin SoC Verification Architecture
Jingxin SoC full chip verification architecture:
A senior student from Jingxin told me that a master’s degree studying abroad in country X went to a certain chip giant in a foreign company with a salary of over $200,000! Converted to RMB, it exceeds 140,000, and he is only about 25 years old! Salary exceeds 1.4 million!
The editor went to check the salary on Glassdoor:
ASIC Engineer with 1-3 years of experience has salary quotes of $212K, $200K.
ASIC Engineer with 7-9 years of experience has salary quotes of $311K, $300K.
Of course, specific salaries also depend on each candidate’s level and job matching.
Education and project experience are very important, looking forward to more good news from Jingxin comrades! Stepping out of the country, the world is more exciting! The positive energy of the Jingxin SoC project is so great that the editor is also shocked. I will definitely continue to polish and help Jingxin comrades succeed together!
Jingxin SoC UPF Low Power Design
Full chip UPF low power design (including DFT design)
The Jingxin SoC training camp training project, before low power design, consumed 27.9mW.
After low power design, the power consumption is 0.285mW, a reduction of 98.9%!
Voltage drop check:
Low power check:
Chip layout design V1.0
Chip layout design V2.0
Chip layout design V4.0
The DRC/LVS of low power design has extremely high practical value at the chip top level and is challenging! Unique experience sharing in the industry.
ISP Image Processing
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dpc – Bad pixel correction
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blc – Black level correction
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bnr – Bayer noise reduction
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dgain – Digital gain
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demosaic – Demosaicing
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wb – White balance gain
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ccm – Color correction matrix
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csc – Color space conversion (RGB2YUV conversion formula based on integer optimization)
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gamma – Gamma correction (brightness based on lookup table gamma correction)
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ee – Edge enhancement
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stat_ae – Automatic exposure statistics
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stat_awb – Automatic white balance statistics
CNN Image Recognition
Supports handwritten digit AI recognition:
Simulation results: Simulated recognition of the above images 7, 2, 1, 0, 4, 1, 4, 9
Jingxin SoC 3.0 ISP:
Jingxin SoC V3.0 DFT program:
If you, like me, are eager for progress and want to master the full process of chip design, welcome to join my knowledge star field, grow crazily, and make progress together! Become a chip master as soon as possible!
Jingxin students, I am very grateful for your recognition, trust, and support for Jingxin. Your encouragement makes me very grateful. I will definitely work harder to refine the Jingxin SoC practical course. I promise to achieve zero negative reviews, so that everyone, whether experienced or inexperienced, can grow from the Jingxin training camp!
Recently, students have been asking me about the choice of offers. Seeing everyone getting their desired offers after improving through Jingxin training makes me very happy. Congratulations to everyone for getting their desired offers!