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This article mainly introduces the differences between CPLD and FPGA.
CPLD and FPGA are both composed of logic array modules, but CPLD’s LAB is based on product terms and macro cells, while FPGA’s LAB uses LUT-based logic units.CPLD’s LAB is arranged around a central global interconnect, growing exponentially with the increase in logic quantity in the device.FPGA’s LAB is arranged in a grid array, increasing linearly with device density.CPLD interconnect includes locally programmable arrays and central programmable interconnect.FPGA devices include local interconnect for each LAB, but separate from LAB logic, and also include row and column interconnects that span multiple LABs in the array and across the entire chip.
CPLD
CPLD is based on product-term technology (Product-Term), EPPROM or FLASH technology; directly written programs do not disappear after power-off; can generally be erased hundreds of times, and macro cells are usually below 512. For example, ALTERA’s MAX3000/5000/7000/9000 and CLASSIC series).CPLD can be divided into three structural blocks: programmable logic array LAB (Logic Array Block, composed of several macro cells (LMC, Logic Macro Cell)), programmable internal wiring (PIA), and I/O control block (IO Control Block).The macro cell is the basic structure of CPLD, used to implement basic logic functions. The LMC mainly includes AND arrays, OR arrays, programmable flip-flops, and multiplexers, which can be independently configured for sequential or combinational operation modes.Each macro cell is directly connected to control signals such as GCLK (global clock), OE (output enable), GCLR (clear), and has the same delay. The macro cells are interconnected by fixed-length metal lines, ensuring that the delay of the logic circuit is fixed.A macro cell mainly includes the LAB’s Local Array (logic array), Product-Term Select Matrix (product term selection matrix), and a programmable D flip-flop. Each intersection of the logic array can be turned on through programming to achieve logic, and the product term selection matrix can achieve OR logic. These two parts work together to implement a complete combinational logic. The output can be selected through the D flip-flop or bypass the flip-flop. Therefore, CPLD is very suitable for implementing combinational logic, and with flip-flops, it can also achieve certain sequential logic.The I/O control block is responsible for controlling the electrical characteristics of input and output, such as setting open-collector output, slew rate control, tri-state output, etc.The programmable internal wiring serves to provide an interconnection network between each logic macro cell and between the logic macro cells and I/O units. Each logic macro cell receives signals from the input through a programmable wiring array and sends the macro cell’s signals to the destination. This interconnect mechanism has great flexibility, allowing changes to the internal design without affecting the pin assignment.
FPGA
FPGA is based on Look-Up-Table (LUT) technology, SRAM technology (can be programmed rapidly and repeatedly); directly written programs are lost after power-off; theoretically can be erased over 1 million times; generally requires external EEPROM, can achieve millions of gates. For example, ALTERA’s APEX, FLEX, ACEX, STRATIX, CYCLONE series, and Xilinx’s Spartan, Artix, Kintex, Virtex, UltraScale, UltraScale+ series.FPGA consists of programmable logic function blocks (CLB), input/output modules (IOB), and programmable interconnect resources (PIR), as well as a SRAM-based configuration memory unit.CLB is the basic unit for implementing logic functions, mainly composed of logic function generators, flip-flops, multiplexers, etc. The CLB is primarily made up of LUTs, which are the fundamental logic units of FPGA. The logic circuits we design are ultimately calculated and stored in the lookup table through EDA tools. Each time, the corresponding result is looked up based on the input signal and then outputted. In other words, FPGA works more like a RAM, outputting corresponding data based on different input signals (addresses).IOB mainly consists of input flip-flops, input buffers, and output flip-flops/latches, output buffers. Each IOB controls a pin, which can be configured for input, output, or bidirectional I/O functions, mainly serving as the interface between the logic on the chip and the external pins.The programmable interconnect resources (PIR) include various lengths of wiring segments and some programmable connection switches, enabling various circuit connections through automatic routing, connecting CLBs within FPGA or between IOBs, and forming circuits with specific functions.
CPLD
FPGA
Internal Structure
Product-Term
Look-Up Table
Program Storage
Internal EEPROM
SRAM, external EEPROM
Resource Type
Rich combinational circuit resources
Rich flip-flop resources
Usage Scenario
Combinational logic
Sequential logic
Basic Logic Composition
LAB composed of macro cells
LAB composed of LE or ALM
Establish Logic Function
Product-Sum
LUT or ALUT
Logic Layout
LAB arranged around central global interconnect
LAB arranged in grid array
Interconnect
LAB local and global interconnect
LAB local and row/column/segmented/global interconnect
Integration Level
Low
High
Wiring Structure
Continuous
Segmented
Pin Delay
Timing delay is uniform and predictable
Delay is unpredictable
Confidentiality
Can be encrypted
Generally cannot be confidential
Flexibility of Use
Programmed by modifying the logic function with fixed internal interconnect (programming under logic blocks)
Programmed by changing the routing of internal wiring (programming under logic gates, more flexible)
The latest CPLD processes are also based on SRAM technology, structurally and resource-wise increasingly similar to FPGA. The main difference is that CPLD achieves non-volatile data retention through integrated chip FLASH, while FPGA requires external FLASH loading.
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