Source: Chip Theory
Abstract: Previous articles have mentioned that there are many classification methods for chips, with varieties as numerous as the stars in the night sky, making it impossible to enumerate them all. This article narrows the focus to high-end general-purpose chips, specifically CPUs. We will find that there are also many types of CPU chips, and various “factions” exist, resembling a “martial arts world” of CPU chips, where the instruction set and microarchitecture serve as the faction symbols. What are CPU instruction sets and microarchitectures? Why are instruction sets and microarchitectures the symbols of these factions? This article attempts to explain in simple language.
CPU is the abbreviation for Central Processing Unit, a type of high-end general-purpose chip. It is used in computers and smart devices to command various components to work together efficiently. It is the control center of computers and smart devices, functioning as the brain.
The components of a computer require the CPU to command them, while the components within the CPU also need to be coordinated to function, with the commander being the program. The commands issued by the program to coordinate the internal circuits of the CPU are referred to as instructions. For example, to compute A + B -> C using the CPU, two load instructions must be sent to retrieve A and B from memory to the arithmetic unit; then, an addition instruction is sent to perform the addition; finally, a store instruction is sent to save C back to memory. In this example, two types of instructions are used: load instructions and addition instructions.
In fact, a general-purpose CPU needs to perform various calculations, reasoning, judgment, and control tasks, requiring a collection of instructions that can range from dozens to hundreds. The collection of various instructions for a CPU is called the CPU instruction set. The instruction set determines how the CPU operates and its corresponding internal hardware architecture, which is referred to as the CPU microarchitecture. The instruction set and microarchitecture form the core intellectual property of a company after developing a new CPU. The instruction set is the top-level design specification for the CPU, while the microarchitecture is the physical implementation of this specification, which can vary in its implementation methods. The generally referred to CPU architecture encompasses both the CPU instruction set and microarchitecture.
Figure 1. A new instruction set and microarchitecture can create a new faction in the CPU chip realm.
Figure 1 illustrates the relationship between instruction sets, microarchitectures, CPU chips, and chip user groups. It can be seen that developing a new instruction set and microarchitecture is akin to establishing a faction in the CPU chip martial arts world. Specifically, if Company A develops a new CPU, it means creating a new instruction set and microarchitecture, not only forming user group A for Company A’s CPUs but also allowing Company A to license other companies to develop CPUs, forming corresponding user groups B, C, D, etc. A new instruction set and microarchitecture can develop a family of CPU chips and create a user cluster, much like establishing a faction in the martial arts world. If the instruction set and microarchitecture are well designed, the CPU’s performance will be good, leading to a larger user base and more followers, and the faction will thrive.
Figure 2. The instruction set is the link between software and hardware.
Figure 2 indicates that the instruction set is the link between software and hardware. Whether it is application programs or system code in the operating system, they are ultimately compiled into machine code programs that can be executed within the CPU chip, conforming to the instruction set specifications. The instructions in the machine code program control the internal components of the CPU to work together efficiently, thereby enabling the overall functionality of the CPU, which in turn controls the operation of the entire system. The instruction set is the legal code that system software and hardware engineers adhere to. Only by following this code can the software written by software engineers run on different models of hardware systems. Hardware engineers can develop hardware systems that can run existing application software.
Having discussed many concepts and analyzed their relationships, if it is still unclear, let’s look at three representative examples of CPU instruction sets and microarchitectures. The first is the MCS-51 instruction set, representing microcontrollers or MCUs. The second is the x86 instruction set, representing complex instruction set computers (CISC). The third is the ARM instruction set, representing reduced instruction set computers (RISC). The purpose of citing these instruction sets and microarchitectures is not for research but to showcase them, aiming to give readers a macro impression of the faction symbols of CPU chips—the instruction set and microarchitecture.
Why is the MCU instruction set presented alongside the CPU instruction set? Let’s first understand the relationship between MCUs, CPUs, and SoCs. MCU is the abbreviation for Micro Controller Unit, a type of low to mid-range general-purpose chip primarily used for controlling small to medium electronic products and systems. SoC stands for System on Chip. MCUs, CPUs, and SoCs are not strictly delineated, but after studying the characteristics of the three, you can clearly distinguish them.
The common characteristic of the three: they are all the control centers of intelligent electronic products and systems, and they all follow instruction sets and microarchitectures. The differences: MCUs generally have 4-bit, 8-bit, and 16-bit microarchitectures with not very high operating frequencies. They handle more control tasks and fewer computational and information processing tasks. Compared to CPUs, they integrate some external interfaces and functional components on a single chip. CPUs generally have 16-bit, 32-bit, and 64-bit microarchitectures with very high operating frequencies, focusing more on processing speed and computational power, with few external interfaces and functional components integrated on a single chip. SoCs place greater emphasis on the system integration of a single chip, with various width microarchitectures, operating frequencies, and integration levels. Single chips can contain multiple external interfaces and functional components.
The difference between MCUs and CPUs lies in their processing capabilities, with MCUs leaning towards control and CPUs towards computation. The processing capability of SoCs can vary; if more external interfaces and functional components are integrated into an MCU or CPU chip, it becomes a SoC chip.
1. The Three Representatives of Instruction Sets and Microarchitectures
Based on the reasons above, and since ARM CPUs are typically embedded in SoC chips, this article selects MCS-51 as the representative instruction set for MCUs, x86 as both the representative of CISC instruction sets and CPU instruction sets, and ARM as the representative of RISC instruction sets and SoC instruction sets, with brief introductions and showcases below.
1. MCS-51 Instruction Set and Microarchitecture
The MCS-51 instruction set was developed by Intel around 1980 for microcontrollers. This instruction set includes five major categories: data transfer, bit manipulation, logical operations and transfers, arithmetic operations, and control transfers, totaling 111 instructions (Figure 3). The corresponding microarchitecture for this instruction set is shown in Figure 4.
By adding, removing, or changing the hardware of this microarchitecture, Intel has developed a series of microcontroller chips compatible with the MCS-51 instruction set, totaling 16 models (Figure 3). Additionally, Intel has opened the MCS-51 instruction set and microarchitecture to many companies, allowing them to produce microcontrollers compatible with the MCS-51 instruction set. These companies include ATMEL, PHILIPS, NXP, OKI, and others from Japan, Taiwan, and domestic firms. Consequently, MCS-51 microcontrollers are widely used globally. The MCS-51 has opened up a large-scale and widely used family of microcontrollers.
Figure 3. MCS-51 Microcontroller Instruction Set (Source: Wuyou Document)
Figure 4. MCS-51 Microcontroller Internal Microarchitecture (Source: Baidu Encyclopedia)
Figure 5. MCS-51 Microcontroller Family (Source: Reference Material 5)
2. x86 Instruction Set and Microarchitecture
In 1978, Intel developed a 16-bit CPU named i8086 and also developed a matching math coprocessor, the i8087. These two chips use a compatible instruction set, and the instruction set for mathematical calculations such as logarithms, exponents, and trigonometric functions formed what is commonly referred to as the x86 instruction set today. Over the past 40 years, Intel has successively developed i80286, i80386, i80486, Pentium series, Core series, and other subsequent CPU models. In developing these CPU chips, Intel has continued to use the x86 instruction set to maintain forward software compatibility, adding extension instructions such as 286, 386, 486, Pentium, Pentium II, as needed to improve CPU functionality and performance. “New for three years, old for three years, patching and fixing for another three years,” it can be said that the x86 instruction set is a model of continuous evolution and increasing complexity, thus embodying the true essence of a complex instruction set (CISC).
The x86 instruction set includes data transfer, logical operations, shift operations, program control, arithmetic operations, string operations, processor control, 286 extensions, 386 extensions, 486 extensions, Pentium extensions, and Pentium II extensions, totaling over 190 instructions (Figure 7). Figures 8 show examples of the CPU microarchitectures for Intel Core and AMD K8.
Intel and AMD are the two largest developers of x86 instruction set CPU chips globally. Intel has hundreds of CPU models that belong to the x86 series. Additionally, with over 80 compatible x86 CPUs from AMD, the lineup of x86 instruction set CPU chips is quite impressive (Figure 10). The CPUs from both companies continuously iterate and upgrade, competing with a wide variety of models, forming a remarkable trajectory of CPU product development.
Figure 7. x86 CPU Instruction Set (Source: Reference Material 1)
Figure 8. Examples of Two Microarchitectures of x86 CPUs (Source: Reference Material 3)
Figure 9. Diagram of x86 CPU Chip Models Developed by Intel and AMD (Source: Network Data Compilation)
3. ARM Instruction Set and Microarchitecture
ARM was established in 1990 and is a leading provider of CPU IP (Intellectual Property) globally, with over 95% of smartphones and tablets worldwide using ARM architecture processors. ARM does not design or sell CPU chips itself but sells and licenses a series of CPU IP based on the ARM architecture to other companies. ARM licensing is broadly divided into three types: architecture licensing, core licensing, and usage licensing, with this article focusing only on the first two. Architecture licensing requires a high level of expertise from the design team and is expensive, making it suitable only for large companies, while small and medium enterprises generally opt for core licensing.
Architecture licensing (also known as instruction set licensing) allows users who have purchased the rights to design and manufacture ARM processors at the architecture level to modify the ARM architecture starting from the entire instruction set and microarchitecture, even reducing or extending the ARM instruction set to achieve better performance, lower power consumption, and lower costs tailored to their needs. Companies with ARM architecture licenses include Qualcomm, Apple, Samsung, Microsoft, HiSilicon, and others.
Core licensing (also known as solution licensing) allows users to apply the ARM core (IP core) they have purchased to their designed chips, but users cannot modify the ARM core. Many companies hold core licenses, including Texas Instruments, Broadcom, Freescale, Fujitsu, and numerous domestic small and medium chip design companies.
Figure 10 shows the ARM instruction set. The ARM instruction set includes jump instructions, data processing, multiply-accumulate instructions, PSR access, load/store instructions, data exchange, shift instructions, and coprocessor instructions, totaling 50 instructions (of which 16 are ARM instructions, 18 are Thumb instructions, and 16 are Thumb-2 instructions). Including 15 control pseudo-instructions, there are a total of 65 instructions. Figure 11 displays a microarchitecture of an ARM core that is available for core licensing, named ARM Cortex A9.
Over 1500 companies worldwide have been authorized by ARM to develop and produce processors based on the ARM architecture and SoC chips containing ARM cores. Figure 12 is a logo map of users, tool vendors, and partners who utilize ARM architecture processor technology. The ARM CPU faction dominates the mobile communication field and is penetrating into other areas, including the Internet of Things, desktop computers, and servers, causing great concern for Intel, the leader of the x86 CPU faction.
Figure 10. ARM CPU Instruction Set and Function Description (Source: Free Document Network)
Figure 11. ARM Cortex A9 Microarchitecture and Single-Core Interface (Source: Reference Material 11)
Figure 12. Logo Map of Users and Partners Utilizing ARM Architecture Processor Technology (Source: Reference Material 11)
2. The Instruction Set Factions in the CPU Chip Martial Arts World
1. MCU Instruction Sets
As a reduced version of CPUs and SoCs, MCUs also have instruction sets and microarchitectures, serving as the control center for intelligent electronic products and systems. Thus, they can be included in the CPU chip martial arts world, allowing readers to see the types of MCU instruction sets.
The instruction sets in this faction include: Zilog’s Z80 instruction set, Intel’s MCS-51 instruction set, MicroChip’s PIC instruction set, ATMEL’s AVR instruction set, TI’s MSP430 instruction set, Motorola’s 68K, ARM’s ARM-Thumb, and more.
2. CISC Instruction Sets
CISC instruction sets are also known as complex instruction sets. CISC refers to Complex Instruction Set Computer. In CISC instruction processors, each instruction is executed serially in sequence, and the operations within each instruction are also executed serially. The advantage of sequential execution is simple control, but the utilization of various parts of the computer is not high, and execution speed is slower.
The instruction sets in this faction include: Intel’s x86 instruction set (x86, x86-64, IA-32, IA-64, etc.), AMD’s compatible x86 instruction sets (x86, AMD64, etc.), and VIA’s compatible x86 instruction sets (x86, AIS, etc.).
3. RISC Instruction Sets
RISC instruction sets are also known as reduced instruction sets. RISC refers to Reduced Instruction Set Computing. It developed from CISC instruction systems, as the frequency of using various CISC instructions is quite uneven. The most frequently used ones are simple instructions, which only account for 20% of the total instruction count, yet appear 80% of the time in programs. Complex instruction systems inevitably increase the complexity of microprocessors, and the instruction decoding and execution processes are complicated and time-consuming, which lowers computer speed. RISC-type CPUs emerged in the 1980s. Compared to CISC-type CPUs, RISC-type CPUs not only simplify the instruction set but also adopt superscalar and superpipeline structures, significantly increasing parallel processing capabilities. RISC instruction sets are the future direction for high-performance CPUs. RISC’s instruction formats are unified, with fewer types and fewer addressing methods than complex instruction sets. Naturally, processing speed improves significantly.
The instruction sets in this faction include: DEC’s Alpha instruction set, MIPS’s MIPS instruction set, Sun’s SPARC instruction set, IBM’s PowerPC instruction set developed in collaboration with Apple and Motorola, IBM’s POWER server CPU instruction set, ARM’s ARM32 and ARM64 instruction sets, and the open-source RISC-V instruction set.
4. EPIC Instruction Sets
EPIC instruction sets are also known as explicitly parallel instruction sets. EPIC is the abbreviation for Explicitly Parallel Instruction Computing. There has been much debate about whether EPIC is the successor to RISC and CISC systems. In terms of EPIC systems, it is more like an important step for Intel’s processors to transition to RISC systems. CPUs designed with EPIC technology perform much better with Windows applications than with Unix-based applications under the same host configuration.
Intel’s Itanium server CPU, which uses EPIC technology, is a 64-bit processor and the first in the IA-64 series.
Figure 13. Classification of Popular CPU Instruction Sets Worldwide
3. Realizing the Dream of Autonomous and Controllable CPUs
To develop domestically controllable CPUs, the first step is to solve the issue of autonomous control over instruction sets and microarchitectures, followed by software ecology and production issues. Figure 14 lists the main domestic CPU instruction sets and their technical sources, which form the basis for developing domestically controllable CPUs, and these resources have received significant attention from the industry. It is hoped that the government can plan and coordinate at a high level, increase financial support, and achieve the dream of domestically controllable CPUs through joint efforts in the industry.
Figure 14. Main Domestic CPU Instruction Sets and Technical Sources (Source: Compiled from Reference Material 9)
How to achieve autonomous and controllable CPU chips in China can be summarized in several recognized approaches: First, purchase popular CPU architecture licenses to develop domestic CPU products; Second, leverage the open-source CPU instruction set RISC-V to pursue the path of self-reliance for domestic CPUs. Third, utilize existing controllable CPU architectures, increase investment and R&D efforts, and fill the gaps in domestic CPUs. Fourth, establish new CPU architectures and pursue the path of self-reliance in domestic CPU development. The ultimate goal is to develop domestic CPUs that are safe, autonomous, and controllable, and the methods can be diverse; it is not necessary to rely solely on creating everything from scratch, nor must one establish a new CPU faction.
1. Purchase popular CPU architecture licenses to develop domestic CPU products.
Currently, most domestic MCU, CPU, and SoC chip R&D follows this approach. Previously, this path has been quite smooth, with domestic chip design sales achieving double-digit growth for many years, expected to exceed 380 billion yuan in 2020. Most companies adopt the method of purchasing licenses, using popular foreign CPU architectures in their self-developed CPU chips, including several SoC chips developed by Huawei HiSilicon, all based on ARM architecture. Since the US-China tech war, everyone has realized this is a self-reliant but uncontrollable path for CPU development.
2. Utilize the open-source CPU instruction set RISC-V to pursue self-reliance for domestic CPUs.
The US’s suppression and blockade of China’s chip industry have led the industry to place hopes for developing autonomous and controllable domestic CPUs on the open-source instruction set RISC-V, which may be the most promising path currently. The reason is that the RISC-V architecture is relatively mature, with excellent performance, having undergone many commercial application verifications. Moreover, there is a certain talent and technology accumulation domestically. People believe that RISC-V has the most potential to change the current landscape dominated by ARM and x86 in the CPU chip realm, significantly impacting ARM’s dominant position in the consumer and IoT embedded CPU markets. RISC-V is the dawn of domestically autonomous and controllable CPUs. The only shortcoming of RISC-V currently is the lack of a complete software ecology, which requires the collective effort of industry peers.
3. Utilize existing controllable CPU architectures, increase investment and R&D efforts, and fill the gaps in domestic CPUs.
Some domestic companies have successively inherited the intellectual property rights of some old foreign CPU architectures years ago, some companies have obtained permanent licenses for relatively mature CPU architectures, and some have independently created CPU and GPU architectures. For example, Alibaba Pingtouge (acquired Zhongtian Micro), Suzhou Guoxin, Zhongsheng Hongxin, Shenzhen Zhongwei, etc. Huawei HiSilicon has also obtained a permanent license for the ARM v8 architecture, all of which provide a solid foundation for developing domestically controllable CPUs. It is recommended that the government and enterprises increase investment and R&D efforts, innovate and develop on these CPU architecture bases, continuously improve the software ecology, and seize the opportunity for domestic replacement and filling gaps to achieve iteration and technological advancement of domestic CPU products.
4. Establish new CPU architectures and pursue self-reliance in domestic CPU development.
This is equivalent to designing a new CPU and establishing a new instruction set and microarchitecture. This is the most challenging path. The challenges manifest in two aspects: First, whether the newly designed CPU can possess advanced performance and functionality, efficiency, and cost-effectiveness; Second, how to quickly establish the software ecology for the new CPU, including assembly and high-level language programming tools, system development verification tools, etc. Building a software ecology takes time, requires a market, and necessitates the collaboration of R&D teams and users. Moreover, establishing a CPU industry faction and allowing it to thrive is not an easy task. Therefore, many people are not optimistic about this path.
Conclusion: 1. Instruction sets are the link between software and hardware; software in electronic products, whether high-level language or assembly, ultimately translates into a series of instructions that command the hardware components to work together, with hardware designed to complete the tasks of these instructions. 2. Instruction sets are the legal code that software and hardware engineers adhere to; only by following this code can the developed software run compatibly on different models of hardware. 3. Instruction sets are the symbols of the CPU chip martial arts factions; company names and product names are merely aliases. Only when instruction sets are the same can products be compatible and interchangeable. Only when everyone recognizes this instruction set and is willing to invest in this faction to continuously improve the software ecology can the user base grow and the faction thrive. 4. Developing domestically controllable CPUs, the most challenging aspect is building the software ecology for the CPUs. If we view the CPU instruction set as the faction symbol, then building the software ecology is akin to creating the faction atmosphere and expanding its influence.
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