UART Transceiver Module Design – 01

UART, as a type of asynchronous serial communication protocol, operates by transmitting data one bit at a time. Each bit has the following meanings:

Idle Bit: When there is no data transmission, the voltage level on the transmission line is high, indicating an idle state.

Start Bit: When data transmission begins, a low voltage of 1 bit width is sent to indicate the start of data transmission, known as the start bit.

Data Bits: The actual data to be sent, which can be between 4 to 10 bits wide. Data is sent starting from the lowest bit outward one bit at a time.

Parity Bit (optional): After the data is sent, a parity bit is sent to verify the correctness of the data transmission.

(Even Parity: The number of 1’s plus this bit should be even

Odd Parity: The number of 1’s plus this bit should be odd)

Stop Bit: A high voltage stop bit is sent at the end.

The width of each UART bit is determined by the baud rate, which is the number of data bits sent per second. Common baud rates include 9600, 19200, 115200, etc.

This design code link: https://pan.baidu.com/s/1VJoSPJRSHYMhmx3rs2t4IA

Extraction code: jsak

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The UART characteristics designed in this example are:

(1) No parity check is supported, hence no parity bit.

(2) Data bit width is fixed at 8 bits, not configurable.

(3) Supports configurable input clock and baud rate.

The schematic is as follows, divided into two main modules: one data receiving control module (Receive_Control) and one data sending control module (Send_Control):

Port Description:

Both the receiving control module and the sending control module have a baud rate clock generation module (BaudRate_set), which is used to divide the circuit input clock (clk) to generate a baud rate clock for data receiving and sending control.

As can be seen, the BaudRate_set module has an enable control signal; the module only operates when the enable signal is high. In the sending control module, the corresponding enable is pulled high only when data is being sent; in the receiving control module, the corresponding enable is pulled high only when data is detected as incoming. This is to reduce power consumption.