The Complete Set of Neural Network DSP Cores Finally Comes Together

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First, let’s look at the news:

“SANTA CLARA, Calif., May 3, 2017 – VeriSilicon Holdings Co., Ltd. (VeriSilicon), a Silicon Platform as a Service (SiPaaS®) company, today announces VIP8000, a highly scalable and programmable processor for computer vision and artificial intelligence. It delivers over 3 Tera MACs per second, with power consumption more efficient than 1.5 GMAC/second/mW and the smallest silicon area in the industry with 16FF process technology.”

“May 4, 2017, Shanghai, China – Cadence (NASDAQ: CDNS) today officially announced the industry’s first standalone complete neural network DSP — Cadence® Tensilica® Vision C5 DSP, optimized for applications requiring high neural network computing capabilities such as visual devices, radar/optical radar, and fusion sensors. With a computing capability of 1 TMAC/s, the Vision C5 DSP is fully capable of handling all neural network computing tasks.”

With VeriSilicon and Cadence successively releasing DSP IPs that support AI (neural networks), along with CEVA and Synopsys, all major DSP IP vendors have now entered the fray. Previous articles in the series “Machine Learning Solutions from Processor IP Vendors” have introduced the solutions from CEVA and Synopsys. Today, let’s take a look at the solutions from VeriSilicon and Cadence.

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The DSP IP launched by VeriSilicon is numbered VIP8000, and currently, there is no detailed introduction on their website; we can only see its block diagram and main features from the press release.

Image from www.verisilicon.com

From the press release, it can be seen that the VIP8000 does not belong to VeriSilicon’s previous ZSP DSP series, but uses the name of the later acquired Vivante. “The Vivante VIP8000 consists of highly multithreaded parallel processing units, neural network units, and general storage cache units.” From this text, it can be inferred that the Programmable Engine is likely based on Vivante’s GPU, rather than a vector DSP like CEVA’s. This is the most interesting point of this architecture.

The important features of the VIP8000 mentioned in the press release include:

1. Under the 16nm FinFET process, the VIP8000 can provide over 3 Tera MACs of computing power per second, with energy efficiency greater than 1.5 GMAC/second/mW, and the smallest silicon area in the industry.

2. The VIP8000 can directly import neural networks generated by mainstream deep learning frameworks such as Caffe and TensorFlow, and can integrate neural networks into other computer vision functional modules using the OpenVX framework. It supports all current mainstream neural network models (including AlexNet, GoogleNet, ResNet, VGG, Faster-RCNN, Yolo, SSD, FCN, and SegNet) and layer types (including convolution and deconvolution, dilation, FC, pooling and unpooling, various normalization layers and activation functions, tensor reshaping, element-wise operations, RNN, and LSTM functions), aimed at promoting the adoption of new neural networks and new layer types. The neural network unit supports fixed-point 8-bit precision and floating-point 16-bit precision, and supports mixed-mode applications to achieve optimal computing efficiency and accuracy.

3. The Vivante VIP8000’s VIP-Connect interface supports customers to quickly integrate dedicated hardware acceleration units, allowing them to work in synergy with standard Vivante VIP8000 hardware units.

4. This processor is programmed using OpenCL or OpenVX, and adopts a unified programming model across hardware units, including customer-specific hardware acceleration units. All hardware units work simultaneously, sharing cached data, which can significantly reduce bandwidth.

5. To better serve embedded products in different market segments, the Vivante VIP8000 can be flexibly configured, with its parallel processing units, neural network units, and general storage units being scalable, and the ACUITY SDK providing training and a complete set of IDE tools.

The first point should be the biggest highlight of the VIP8000, but the description in the press release is too vague. Until we see more detailed analysis and data support, it is difficult to evaluate; just take a look for now. The other features and tools are basically standard for this type of IP, and there isn’t much new (it seems to support more types of NN). As for the tools, without personal experience, it is impossible to know what pitfalls there might be.

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The title of Cadence’s press release is “Cadence Unveils Industry’s First Neural Network DSP IP for Automotive, Surveillance, Drone and Mobile Markets.” The first thing I noticed is the claim of being the first; previously, both CEVA and Synopsys have launched DSP IPs that support neural networks, so where does this “first” come from? Upon closer inspection, Cadence’s Vision C5 DSP is specifically designed for neural network processing, rather than using a Vision DSP + NN Engine like previous solutions. In this sense, it can also be considered the first.

Image from ip.cadence.com

From the above image, it is clear that the Vision C5 DSP is indeed specifically designed for NN, “Heavy-Duty Always-On NN.” Traditional CV is handled by the Vision P5/P6 DSP. This also means that future SoCs using Cadence’s solution may need to use two DSPs simultaneously, such as P6+C5, which, compared to CEVA’s Vision DSP + NN Engine tightly coupled solution, the overall effect remains to be seen. However, for different applications, this also provides an additional choice.

Compared to VeriSilicon, Cadence’s website already has more detailed information about the Vision C5 DSP. The following table compares the P5, P6, and C5 DSP cores. A key metric for C5 includes 1024 8×8 MACs (or 512 if operating in 16-bit).

Image from ip.cadence.com

The block diagram of the C5 DSP is as follows:

Image from ip.cadence.com

The specific features of the C5 processor are as follows:

1. A chip area of less than 1mm² can achieve a computing power of 1 TMAC/s (throughput improved 4 times compared to Vision P6 DSP), providing extremely high computing throughput for deep learning cores.

2. 1024 8-bit MACs or 512 16-bit MACs ensure excellent performance for both 8-bit and 16-bit precision.

3. A VLIW SIMD architecture with 128-way 8-bit SIMD or 64-way 16-bit SIMD.

4. Designed for multicore, achieving NxTMAC processing capability with minimal resource cost.

5. Built-in iDMA and AXI4 bus interface.

6. Uses a proven software toolkit consistent with Vision P5 and P6 DSPs.

7. Based on the industry-renowned AlexNet CNN Benchmark, the Vision C5 DSP’s computing speed is up to 6 times faster than the fastest GPUs in the industry; for the Inception V3 CNN benchmark, there is a 9-fold performance improvement.

1024 MACs and some dedicated NN accelerators are not too many. From public information, this number is slightly more than CEVA and Synopsys’s NN Engine. From the block diagram, the C5 DSP is still based on Cadence’s previous DSP architecture, rather than a specially designed NN accelerator, so the final implementation efficiency of this architecture remains to be seen.

For analysis of this information, you can refer to my previous articles: Machine Learning Solutions from Processor IP Vendors – Synopsys and Machine Learning Solutions from Processor IP Vendors – CEVA. These articles provide detailed explanations on how to view the features of these DSP cores, so I won’t elaborate further here.

So far, all major DSP IP vendors have launched their own neural network processor solutions (not counting ARM, this big player in IP). Whether new or old architectures, it shows everyone’s emphasis on this direction. The news in the past two days gives me the feeling that the good show has just begun, and I can already smell the smoke of competition.

T.S.

The cover image is from the internet, copyright belongs to the original author

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