What does it mean? Is Old Wu trying to incite everyone to take a detour? Is working impossible? Actually, what Old Wu means by copper thieving refers to Copper Thieving.
Copper Thieving literally means copper that has thieving behavior, commonly known in the industry as balance copper, also referred to as plating copper, which refers to copper balance blocks added in the outer layer graphic area of multilayer PCBs, PCB assembly auxiliary strips, and manufacturing panel auxiliary strip areas.
What is the use of Copper Thieving? In the PCB production process, during the outer layer plating process, it balances the plating current to avoid inconsistent current during the plating process, leading to uneven copper thickness in the finished product. This means that during the plating process, the plating current is taken away from the copper foil dense area, allowing for a more even current distribution, thus avoiding uneven copper thickness in the finished product.
Why mention this? Recently, a friend sent Old Wu a prototype development board said to be from the first generation iPhone. The board is very beautiful, especially with many small square copper blocks covering its surface, giving it a very artistic feel, immediately reminiscent of Louis Vuitton’s classic checkerboard pattern.
These small copper blocks look like copper plating but are different; they consist of many very small independent square copper blocks, each copper block is an independent unit, and does not electrically connect with other components on the circuit board. For example, as we know, a large area of copper on a PCB must be connected to the main 0V reference plane through metallized vias spaced at least 1/10 of the concerned frequency’s wavelength.
Suspended large-area copper foil is equivalent to a Patch Antenna, as shown in the figure below, the common-mode current on the board can easily enter the antenna, causing electromagnetic radiation issues 
Inadequate large-area copper holes lead to high impedance, causing resonance, which also radiates electromagnetic waves 
In fact, for PCBs with high-speed digital signals and low impedance return planes, the outer layer copper plating does more harm than good, note, Old Wu is saying this under the premise of 【high-speed digital signals】 and 【low impedance return planes】, this premise is important. If it is a double-sided board or high impedance analog circuit, copper plating is still beneficial.
For multilayer PCBs with low impedance return planes, high-speed digital signal return will directly take the path of lowest impedance rather than the shortest straight distance, thus minimizing resistance, meaning that most return current is concentrated on the reference plane corresponding to the signal. The smaller the distance H between the trace and the reference plane, the more concentrated the return current is in the area corresponding to the trace. In other words, the area of return current diffusion is relatively small, which can reduce crosstalk. The tighter the return coupling, the more it can reduce differential mode radiation. Therefore, the preferred method to improve the EMC performance of surface traces is through reasonable stack structure design, keeping high-speed signal transmission lines as close as possible to the reference plane, allowing return to flow from the low impedance reference plane rather than constructing another return path through copper plating to compensate, meaning that copper plating is irrelevant. If you want to copper plate, you also need to drill metallized vias to connect to the 0V reference plane, and in the corners, copper plating can easily form unintended antennas. Once vias are drilled, each via will occupy the already crowded inner layer routing space, as well as the integrity of the main power/0V reference plane. The increasing number of IC pins and routing layer change vias have already turned the plane into a sieve, and adding a pile of holes for outer layer copper further worsens the situation for maintaining low impedance on the main plane. At the same time, if copper foil is improperly handled and is too close to transmission lines that require controlled impedance in localized areas, it can also cause a sudden change in transmission line impedance, leading to signal reflection and integrity issues.
Of course, if there is relatively complete copper foil on the outer layer, this copper foil can provide some shielding effect or improve the inter-layer capacitance of the PCB, which helps enhance EMC performance. However, for cases dominated by high-speed digital signals, the outer layer is filled with components and fan-out vias, making it difficult to form a complete plane.
For two-layer boards, the traces are too far from their reference plane, and the 0V reference plane also needs to route, making it hard to maintain the integrity of the plane. In this case, copper plating in the empty areas of the board and adding more holes to connect to the 0V reference can construct a low impedance return path, which is still very beneficial for improving EMC performance.
For areas with low impedance reference planes for high-speed digital signal traces, Old Wu does not recommend copper plating on the outer layer. However, if the outer layer has too low a copper rate, such as in the BGA area of the main control and surrounding DRAM, where the copper foil density is relatively high, while other areas have relatively low copper content, the uneven copper distribution during the plating process can lead to excessive current density in the BGA area, causing uneven copper thickness in the plating product. For example, differential pairs with uneven copper thickness can adversely affect impedance control, and large differences in copper thickness on BGA pins can also impact SMT yield, etc.
The solution is to improve the balance of copper foil distribution density. These checkerboard-like small copper blocks are a good choice; of course, there are also small dot shapes. Each unit is physically much smaller than 1/4 of the wavelength, making it difficult to form effective radiating antennas, and there is no need to drill vias to connect to the 0V reference plane, thus not occupying the already crowded inner layer routing space. The only thing to note is that there should be no impedance-controlled lines below Copper Thieving; these copper blocks can cause impedance discontinuity. Also, do not place them too close to areas requiring ESD protection.
The board factory will add balance copper blocks based on the residual copper rate calculated by CAM software and send it to you for confirmation. At this time, it is important to check whether these copper blocks will adversely affect impedance. Of course, it is best to add them yourself to avoid communication errors with the factory’s technical staff. Mainstream EDA software such as Cadence Allegro 16.6 and later versions, Mentor PADS Professional, etc., have added the function to add Copper Thieving.
One more thing to add is that Copper Thieving specifically refers to copper blocks on the outer layer. Thieving means to steal the plating current to make the outer layer copper thickness more uniform. The same copper blocks used in the inner layer do not have the effect of Thieving; instead, they are balance copper, preventing excessive area of resin in the inner layer from causing voids or bubbles during lamination, and balancing the mechanical stress differences produced by different layers of copper foil when heated. The copper blocks remain the same; they just serve different purposes.
Below are some examples of applying Copper Thieving on the outer layer, enjoy the art of copper thieving on PCBs 
