Q: What is the progress and mass production schedule for Broadcom’s main cooperative chips?
A: Broadcom has a total of seven main and potential cooperative customers, each with different progress and mass production schedules. Among them, Google, Meta, and OpenAI are mass production customers this year. Google has already mass-produced multiple generations of chips and will launch the TPU V6P in the third quarter of this year; Meta’s chip is tentatively scheduled for mass production in September. XAI and Anthropic are expected to be mass production customers next year. The ByteDance project is currently on hold, and the mass production time is yet to be determined. Apple plans to decide in the fourth quarter of this year whether to adopt Broadcom’s chips.
Q: Is there an expected shipment volume for Google’s TPU V6 series chips? What is the specific launch time?
A: Google TPU V6E has already been launched, and the overall forecast shipment volume for Google’s chips this year is close to 2 million units, with the TPU V5 series accounting for 1.4 million units and approximately 400,000 units for the standalone TPU V6 series, including V6E. V6P is expected to ship 100,000 to 200,000 units and is planned for release in the third quarter of this year.
Q: What is the reason for the relatively low quantity of TPU P series chips?
A: The P series chips are primarily used for training tasks, while Google’s chip architecture is mainly focused on inference tasks, resulting in a ratio of training chips to inference chips of about 2:1. Since there are relatively more inference chips, this leads to a lower quantity of P series chips.
Q: Is the overall shipment volume of V6E chips this year about 500,000 units?
A: The overall shipment volume of V6E chips this year is approximately 500,000 units. This situation is mainly due to two reasons: first, the product has just been launched and has not yet entered the rapid ramp-up phase; second, from a cost perspective, Google is still continuing to use V5 series chips, which has somewhat affected the shipment volume of V6E.
Q: What is the pricing model for V6P and V6E chips?
A: The pricing model for V6P and V6E chips mainly includes four parts: wafer costs, royalties for third-party IP modules in the chip, technical support fees, and upfront R&D costs. These costs together constitute the pricing system for the chips.
Q: Is an upfront payment required for the initial R&D costs of chip design?
A: The initial R&D cycle for chip design is relatively long, so a certain amount of deposit is required, usually around 20%-30%. After the design cycle ends, the remaining costs need to be paid, and if it enters the mass production stage later, this upfront payment can also be deducted from the price of the mass-produced chips.
Q: What are the subsequent costs per unit for mass production, taking V5E or V6E as examples?
A: Currently, the average price per unit for V5E during mass production is about $3,000 to $3,500, while the price for V5P is higher, around $6,000. There are price differences for different models of chips during mass production.
Q: Are V5/V5P products designed by Broadcom, who also bears the wafer costs and sells them?
A: No, Broadcom is only responsible for designing V5/V5P products and bearing the wafer costs. Once the product design is completed, it will be directly delivered to Google and is not responsible for selling the product.
Q: What is the gross margin level calculated at a million-unit scale?
A: Calculated at a million-unit production scale, the average gross margin for Broadcom’s chip design business is close to 60%, specifically between 55% and 58%. This gross margin level reflects the profitability of this business.
Q: Why is the gross margin of the chip design business much higher than that of traditional design service companies?
A: The gross margin of the chip design business is higher than that of traditional design service companies mainly due to the complexity of the chips and the level of Broadcom’s involvement in the business. The more complex the chip, the more Broadcom is involved, and the deeper the involvement, the higher the gross margin.
Q: Is Google currently the largest customer of the company’s ETIC business?
A: Google is currently the largest customer of the company’s ETIC business, accounting for nearly 80% of the revenue from this business, highlighting Google’s importance to the company’s ETIC business.
Q: How does the usage of PCBs and optical modules in Google’s related products compare to that of NVIDIA’s previous GPU products?
A: The PCB usage of Google’s TPU V5 and other products is more complex compared to NVIDIA’s GPUs, with PCB layers typically reaching 30 layers or more, using HDI multilayer substrates, and involving three types: mid-boards and interface cards. In terms of optical modules, Google’s TPU V5 and other products require about two 800G optical modules per card, while NVIDIA’s H100 GPUs use a maximum of two 400G optical modules.
Q: What are the differences in optical module specifications between TPU V5 and NVIDIA’s H100/H200 products?
A: TPU V5 requires about two 800G optical modules per card; NVIDIA’s H100 and H200 products mainly use two 400G optical modules. Although some configurations of the S200 model use two 800G optical modules, this is not common, and 400G optical modules remain mainstream. The choice between 800G and 400G optical modules mainly depends on the product’s data bandwidth requirements.
Q: Why are the bandwidth requirements for related products relatively high?
A: The high bandwidth requirements for products are mainly determined by the data interconnection needs between chips. For example, TPUs are usually integrated on the same board and contain multiple chips, while NVIDIA chips often use dual-chip designs. Google chips may be configured with 8-16 chips or even more. The increase in the number of chips significantly raises the data bandwidth requirements, and 400G modules cannot meet this demand, necessitating higher bandwidth modules.
Q: Besides TPU using 800G optical modules, do OpenAI and Meta follow the same path?
A: OpenAI’s chip design path is closer to NVIDIA’s GPU servers, as its chips are mainly used for training, with fewer chips per card. The specific number is adjusted based on data bandwidth requirements: if using 400G optical modules, two modules are needed; if using 800G optical modules, one module suffices. Due to thermal constraints, its requirements are consistent with NVIDIA’s H series. OpenAI’s high dependency on NVIDIA chips means its architecture, graphics card design, chip computing power, and HBM memory size are similar to NVIDIA’s. In contrast, TPUs have evolved towards miniaturization over the years, focusing more on flexible networking and balancing inference and training tasks, resulting in lower power consumption and more flexible networking for Google TPUs; whereas Meta and OpenAI pursue absolute computing power in training tasks, with fewer chips per card, making Google’s TPU more advantageous overall.
Q: If developing training chips, is the development difficulty greater? What are the main reasons for the development difficulty of training chips mentioned by Jensen Huang?
A: Jensen Huang pointed out that the development difficulty of training chips is high, partly because training chips require greater bandwidth and computing power to meet the high data processing demands during training; more critically, they rely on a mature software ecosystem. Since AI developers have long been accustomed to developing in NVIDIA environments, transitioning to new platforms like Meta, OpenAI, or Google presents a high learning barrier, making the adaptation of new chip development environments and platforms the biggest challenge they face.
Q: How significant is the gap in computing power, communication, and networking capabilities between individual chips? Is this the main difficulty?
A: There is a certain gap in computing power, communication, and networking capabilities between individual chips, but these are not the main difficulties. The primary challenge lies in the software ecosystem development environment. In terms of hardware architecture, the designs of Google and other chip designers share commonalities in many aspects, with differentiated optimizations for different models, but the differences and technical barriers at the hardware level are not significant.
Q: What is the specific plan for IC design currently? In the SDK, who dominates the writing of operators and algorithms, the design service company or the large model manufacturers?
A: The IC design plan involves the evolution of collaborative models between both parties. In the past, cloud vendors relied heavily on design service companies to convert algorithms or models into circuit designs due to weak hardware teams. However, in recent years, Google has accumulated talent over nearly a decade, and its chip design team now has the capability to convert algorithms, architectures, and models into circuits, thus shifting the core modules to be completed independently to improve efficiency, while non-core modules such as IO, power management, and other logic units are still handled by design service companies like Broadcom. The dominant party in writing operators and algorithms in the SDK has also changed, with more core parts being led by large model manufacturers.
Q: If large model manufacturers take on more work, and the company only manages circuits, will the company’s gross margin theoretically decline?
A: If large model manufacturers take on more work and the company only manages circuits, the design cycle will shorten, which may not significantly reduce unit time revenue. Although the original development cycle was long, some tasks are now handled by large model manufacturers, shortening the development cycle, but the workload for backend chip wafer production, design services, and after-sales technical support has not decreased. Overall, the company’s revenue gross margin will be affected to some extent, but it can be partially compensated by developing new customers. Due to existing customers developing in-house or outsourcing core aspects, the company’s participation will decrease, leading to a decline in gross margin for Google-related business.
Q: Compared to NVIDIA products, has the PCB usage increased or just the complexity improved?
A: Compared to NVIDIA products, the complexity of PCBs has increased rather than the usage. For example, Google’s chips require a single PCB to integrate 8-16 high-pin-count TPU chips, increasing the interconnection needs between chips, which necessitates adding layers to meet layout and routing resource requirements and using more layers of isolation to ensure signal integrity, thus increasing PCB complexity.
Q: Do the PCB manufacturers currently cooperating with the company include Huadian?
A: The PCB manufacturers currently cooperating with the company include Huadian in China, as well as two or three manufacturers such as Zhen Ding in Taiwan, and one or two other manufacturers in mainland China, with Huadian being one of the cooperating PCB manufacturers.
Q: When is OpenAI’s ASIC chip expected to be launched?
A: OpenAI’s ASIC chip is expected to be launched in the fourth quarter of this year, reflecting its progress in chip R&D.
Q: What are the main highlights of OpenAI’s training chip?
A: Compared to similar chips from Google and Meta, the biggest difference of OpenAI’s training chip is its focus on training scenarios, as its tasks are mainly centered around large models and ChatGPT training, unlike Meta’s design direction that integrates training and inference. This chip has a higher cost in terms of scale, cost, and HBM usage, making it a relatively high-cost product within the ETIC scope, with its design focusing more on meeting high-intensity training demands.
Q: What is the pricing situation for OpenAI’s chip? Does its primary use for inference and training affect the price?
A: OpenAI’s chip has a relatively high cost, with an expected unit price possibly exceeding $10,000, around $10,000. Its primary use for training, which has higher requirements for performance and configuration, also leads to higher costs, thus affecting the unit price, making training chips relatively more expensive.
Q: Is the expected price of OpenAI’s chip similar to the current reduced price of NVIDIA’s H100?
A: The prices of the two are not similar; OpenAI’s chip is expected to be priced around $10,000, while NVIDIA’s H100, after recent price reductions, is priced around $20,000 to $30,000, making NVIDIA’s H100 more expensive.
Q: How many chips are designed internally for this product? Is it a dual-chip package?
A: This product typically adopts a dual-chip design, with the most common architecture being dual-chip, which meets performance requirements while also considering cost and power consumption.
Q: What is the current progress of Meta’s integrated training and inference architecture?
A: The progress of Meta’s integrated training and inference architecture has a clear rhythm and plan, with an expected shipment volume of about 300,000 units this year, and the chips are planned to arrive between late August and early September. Currently, Meta’s training and inference tasks each account for half, so a design scheme integrating training and inference functions in a single chip is adopted. Whether to split training and inference chips in the future is still undecided. Based on the scale demand of its data center, the maximum planned shipment volume for next year may reach 800,000 units.
Q: When is the Meta A70 product expected to go into mass production?
A: The Meta A70 product is currently expected to go into mass production in the third quarter of this year, based on its product R&D progress and market demand.
Q: What is the chip demand volume for Meta this year?
A: Meta’s chip demand volume this year is about 300,000 units, and due to the large scale of its data center, the demand for chips is also considerable, with the maximum planned demand for next year possibly reaching around 800,000 units.
Q: What is the current level of process nodes for mainstream products? Are they basically within 5 nanometers?
A: The mainstream products launched this year are still mainly at the 5-nanometer process. However, technology is continuously evolving, and it is expected that new products from V7, Meta, OpenAI, etc., will develop towards 4-nanometer or 3-nanometer processes next year, further enhancing the process nodes.
Q: Is there any uncertainty in new customer cooperation?
A: There is some uncertainty in new customer cooperation, as Apple has not yet signed a contract with the company, and the cooperation relationship is still not finalized, which reflects one aspect of uncertainty in new customer cooperation.
Q: Is the demand volume for Apple’s business expected to be large?
A: As an application platform, Apple’s business demand scale needs to be assessed based on specific cooperation situations. Currently, Apple has not signed a contract with the company, and the cooperation relationship is still not finalized. From a business perspective, Apple focuses on its product ecosystem, having previously procured 100,000 TPU V5P chips from Google when launching the iPhone 16 last year; its platform’s AI capabilities are continuously increasing, generating a large amount of data daily. Apple hopes to empower terminal products to achieve AI functionality but focuses on its product ecosystem without expanding external large model business, so the size of its demand still depends on future cooperation situations.
Q: Are there any other potential large customers besides Apple?
A: Besides Apple, the company is currently negotiating with other potential large customers, one of which is a Japanese company. This company previously procured a large number of chips from NVIDIA for building data centers and plans to customize AI chips for its own data center based on the need to reduce reliance on NVIDIA chips. However, the current cooperation is in the early negotiation stage, and the decision time is expected to be later than the Apple project, possibly needing to wait until next year to determine whether to cooperate.
Q: Why has Broadcom received more AI chip orders while Maywell and AMD have not? What are its comparative advantages?
A: Broadcom has received more AI chip orders while Maywell and AMD have not, mainly due to Broadcom’s multiple comparative advantages. First, based on the long-term accumulation of multiple product lines, it has formed deep chip design experience and optimization capabilities, including improving design performance through self-designed processes and software, with some module performance superior to peers; second, it has rich logic IP resources covering various chip design needs; third, it maintains good cooperative relationships with foundries like TSMC, which can provide exclusive technical support and capacity assurance, thus having a competitive advantage in complex chip design and mass production.
Q: What is Google’s expected procurement volume for next year?
A: Google’s expected procurement volume for next year has two figures; under conservative estimates, it is about 2.5 million units, while under optimistic estimates, it could reach 3 million units. This range reflects expectations for market demand and its own development.
Q: What is Meta’s expected supply volume for next year?
A: Meta’s expected supply volume for next year is 800,000 units, based on its own business development and data center construction needs.
Q: What is OpenAI’s expected procurement volume for next year?
A: OpenAI’s expected procurement volume for next year is about 500,000 units, reflecting its planning for business development and chip demand.
Q: Assuming Google’s chip sales revenue this year is $10 billion, what would the upfront design fee be?
A: The upfront design fees vary for different types of chips. The design fee for inference chips is generally about $200 million, while the design fee for training chips is about $500 million. Assuming Google’s chip sales revenue this year is $10 billion, the upfront design fees can be estimated based on the sales proportion of inference and training chips, and the ratio of design fees to revenue will also vary depending on the type of chip.
Q: Did last year’s AI acceleration chip shipments all come from Google? Were there other customers?
A: Last year’s AI acceleration chip shipments mainly came from Google. Although most of the shipments were contributed by Google, not all came from Google, but the shipment volume from other customers was relatively small.
Q: What were the unit prices of various models of AI acceleration chips last year?
A: Last year’s AI acceleration chips mainly involved the V5 series and V4 models, with different unit prices. The unit price of V5P was close to $7,000, V5E was about $3,000 to nearly $4,000, and V4 was between $6,000 and $6,500. These unit prices reflect the value and market positioning of different models of chips.
Q: How was the shipment volume of V5P, V5E, and V4 last year?
A: The shipment volumes of different models of chips last year varied. V5P, launched in the second half of the year, had an overall shipment volume of less than 400,000 units, of which 100,000 units were supplied to Apple; V4 had a shipment volume of about 100,000 units; and V5E had a shipment volume between 700,000 and 800,000 units. This shipment situation is related to the launch time and market demand of each model of chips.
Q: What is the approximate unit price of Meta’s latest chip?
A: The unit price of Meta’s latest chip is about $8,000, which adopts an integrated training and inference design, and the chip size is larger than that of Apple’s similar products, all of which contribute to its pricing level.
Q: Does ByteDance have annual demand expectations or price information for related products?
A: ByteDance’s annual demand guidance for related products is 600,000 to 800,000 units, but specific price information for these products has not yet been disclosed.
Q: Is the unit price of ByteDance’s chips relatively low?
A: The prices of ByteDance’s chips are similar to those of Meta’s chips, and although ByteDance’s production scale is large, which may affect costs, currently, its unit price is not low and is at a similar level to Meta’s chips.
Q: Why did Amazon choose to cooperate with Marvell despite its large business scale? Is there a possibility of future cooperation with our company?
A: Amazon’s choice to cooperate with Marvell may have various reasons, and currently, Amazon is also evaluating cooperation with our company, indicating a possibility of collaboration, mainly because Amazon’s current performance in training tasks has not met expectations, and it may hope to meet its needs through cooperation with more parties.
Q: Will there be changes in chip architecture next year? Will companies like Meta and OpenAI launch new chips next year? What is the iteration rhythm of their chips?
A: There may be some changes in chip architecture next year. Different companies have different chip iteration rhythms; Google’s chip iteration speed is relatively fast, currently launching one generation per year; OpenAI, being smaller, has a slower iteration speed for training chips, expected to be about one generation every two years; Meta currently plans for one generation every one and a half to two years, and the specific iteration rhythm may accelerate based on the usage of existing chips and model computing power needs. Next year, companies like Meta and OpenAI may launch new chips.
Q: What is the specific type breakdown of Google’s optimistic expected 2-3 million chips next year?
A: Among Google’s optimistic expected total of 2-3 million chips next year, the breakdown of types is as follows: the total for the V7 series is expected to be no more than 600,000 units, mainly with V7E accounting for 400,000 to 500,000 units; V7P is expected to be launched by the end of next year, with a shipment volume of about 100,000 units. In the V5 series, due to the launch of V6E and V7E, the demand for V5E will decrease, with an expected shipment of 300,000 units next year; V5P is expected to have a demand of 300,000 to 400,000 units as V7P has not yet fully replaced it. V6E and V6P will become the main shipment force, with a total expected of 1.6 to 1.8 million units, of which V6E is about 1 to 1.2 million units and V6P about 600,000 units. The shipment planning for each series of chips is closely related to market demand and product iteration rhythm.
Q: What is the value of individual chips in the V6E, V6P, and V7 series?
A: The value of individual chips in the V6E, V6P, and V7 series varies. The average unit price of E series chips is about $4,000, with older V5 chips priced around $3,000 to $3,500 due to their smaller process and area; the newly launched E series chips may reach a unit price of $4,500, later returning to an average level of $4,000. The unit price of P series chips is about $6,000 to $7,000; the unit price of V7P chips is expected to be no more than $8,000, around $7,000. The value differences among different series and models of chips are mainly determined by their processes, performance, and launch times.
Q: Are optical chips in traditional communication chips still declining? How is the growth situation of other traditional chips?
A: Optical chips in traditional communication chips have not shown a declining trend, supported by demand in data centers and optical module fields, maintaining an annual growth of about 10%, although the growth rate has slowed compared to 2022-2023. Other traditional chips have not shown significant declines but are experiencing weak growth, only maintaining single-digit growth. This is mainly due to market saturation and intense price competition; even if there is growth in shipment volume, price declines will still impact revenue and profits, leading to a clear differentiation in growth trends across various segments of traditional chips.
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