【Abstract】 This year’s RISC-V Shanghai Summit had few blockbuster applications, with the core advantage being the reduction in design costs.
Of course, beneath the surface of prosperity, the ecological challenges remain tough. The absence of blockbuster IPs and SoCs, significant gaps in the software ecosystem, a lack of high-end application cases, and severe talent shortages are all issues. IP vendors like Damo Academy are still deeply mired in the awkwardness of scarce deep customers and blockbuster applications.
The industry is still calling for a “product master” to define the scene.
Currently, Baoyungang, Chief Scientist at the Beijing Open Source Chip Research Institute, and Leendert van Doorn, Senior Vice President of Qualcomm, have both proposed moving beyond the simple “ARM alternative” mindset. The true potential of RISC-V lies in the reconstruction of the software-hardware relationship through its open architecture.
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Below is the main text:
Contrary to the disruptive innovation expected by the outside world, the Chinese RISC-V industry may currently be taking a gradual approach that subtly influences the market.
At this year’s RISC-V Shanghai Summit, the observed penetration occurred more at the design architecture level. At the outermost application layer, ordinary users still do not see many variations, with the most obvious manifestation being the absence of blockbuster IPs and SoCs.
Its core value currently lies in the significant reduction of design costs.
Baoyungang, Secretary-General of the China Open Instruction Ecosystem (RISC-V) Alliance and Chief Scientist at the Beijing Open Source Chip Research Institute, calculated during his keynote speech: for developing a 64-core server chip with a production volume of 100,000 units, the traditional development cost is about 750 million yuan, of which IP licensing fees and royalties account for about 250 million yuan, or one-third. However, based on an open-source collaborative development model, companies can save 250 million yuan in R&D costs.
This explains why manufacturers like Yiswei can produce complete machines at lower prices, and the K1 chip from Jindetian can be widely used in general scenarios. Some companies are beginning to attempt product definitions driven by vertical application needs, such as the high-performance chip “Lion Mountain” developed in deep cooperation between Saifang Technology and Super Fusion, which is about to enter mainstream servers. In other words, RISC-V is gradually “nibbling” market share from ARM and x86 rather than “snatching” the market.
01
The Ecosystem Still Needs a Platform
This year’s RISC-V Shanghai Summit attracted significant attention, with over 2,000 domestic and international professional attendees. Chen Jie, Vice Mayor of Shanghai, emphasized in his opening speech that Shanghai will create a RISC-V industry cluster area to foster a better industrial ecosystem.
This goal directly addresses the real challenges behind the prosperity, and Baoyungang pointed out in his speech the four urgent issues that need to be resolved for the RISC-V industry to take root:
First, there is a lack of truly competitive products and solutions, leading to the problem of “loud thunder but little rain”;
Second, the toolbox is not rich enough, far from achieving the effect of “many, fast, good, and economical”;
Third, there is a severe shortage of talent at all levels, including chip design, verification, solutions, and technical support;
Fourth, there are not enough benchmark cases, especially in the server chip and AI chip fields, where high-end application cases are lacking.
A key data point is that in OpenEuler (the open-source Euler operating system), the number of software packages for x86 and ARM exceeds 30,000, while the number of RISC-V software packages is less than 3,000, highlighting the ecological gap.
In this context, RISC-V still has performance and software support gaps.
For decades, optimized software development has favored ARM and x86. Linux support for the RISC-V ISA is continuously improving, but Windows has yet to provide such support, and Android has only just begun development. The lack of mature software support has always been a fatal weakness for many promising architectures, and developers need time to optimize the operating systems, libraries, and compilers for the ISA.
Currently, RISC-V’s advantage lies in the efficiency of embedded applications, but in high-performance computing, architectural innovations such as out-of-order execution, speculative execution, and branch prediction are still in their infancy in RISC-V design.
The true potential and value of RISC-V have yet to be realized.
It is worth noting that at the summit, the materials bag was filled with training flyers, which is a typical sign of early-stage ecological development. The cultivation and construction of the industrial ecosystem indeed need to start with incremental iterations of courses like “RISC-V Embedded Development Practice” and “Introduction to High-Performance RISC-V Processor Design”.
02
Waiting for the Apple Moment
At this summit, the Damo Academy’s XuanTie team released the wide-width Vector Engine XuanTie TITAN, supporting scalable vector lengths from 512 to 4096 bits, enabling instruction-level parallel acceleration. XuanTie has also newly designed the Tensor Processing Engine (TPE), which is a more suitable native architecture for AI, with a GEMM computing execution rate increased to 96.8%, adaptable to real-time training scenarios for large models.
Damo Academy was established in 2017 and has since invested in R&D for the RISC-V architecture, being one of the earliest technical teams involved in this field.
At the summit booth, several applications containing RISC-V IP chips were showcased. For example, the application with Talking Tom seemed a bit confusing, even for children, and the sound prompt for scanning payments felt somewhat redundant.
More critically, the level of competition is intense, and the current average price point for RISC-V IP companies is relatively low. Huawei and Yiswei, which also have internal business needs, are strong competitors.
According to research from ChipFlow Think Tank, previous RISC-V IP vendors like Xinchip can now freely combine various domestic IPs, with prices significantly lower than the $80,000 entry-level ARM version.
This means that companies, including Damo Academy, must compete with ARM and x86 for ecosystem development while also competing on price with less mature peers.
Under this pressure, companies like Damo Academy must seek higher-value breakthroughs.
Of course, Xu Peng, a senior development engineer at Damo Academy, also revealed at the forum that the XuanTie team is advancing edge-side inference optimization and building a higher-performance software ecosystem to support efficient deployment of mainstream models like LLaMA, attempting to establish a differentiated advantage in the AI race.
Additionally, another core IP for achieving high-end SoC products is the consistent on-chip network (NoC). In the early stages of industry development, more attention was paid to CPU core performance, but as product R&D and ecosystem construction progressed, it became increasingly clear that the mutual optimization of native RISC-V CPU cores and NoCs is also indispensable. Therefore, the industry is paying more attention to self-developed NoC IPs. For example, at this summit, Saifang Technology announced that its self-developed large-scale consistent NoC IP—Fang·Xinglu-700 (StarNoC-700) has entered the delivery stage.
More critical breakthroughs await a product design master to bring some shock to the industry.
03
Not Following ARM’s Old Path
In the keynote speech at the summit, Baoyungang, Chief Scientist at the Beijing Open Source Chip Research Institute, made a key point: “If RISC-V is only used as a direct replacement for ARM, it will bury its true advantages.”
This also involves a series of practical issues: if ARM is working well, why would customers switch to RISC-V? What scenarios do RISC-V chips target? What investments are needed for software development on RISC-V chips, and how can developers make money? There are many people in the market who understand ARM solutions, but where can one find those who understand RISC-V technical support?
Essentially, the key breakthrough point for RISC-V should lie in its openness and customizability. Openness allows for the development of open-source toolchains, structurally reducing costs and fostering new business models. Customizability means achieving extreme optimization of hardware and software, lowering development barriers. In the future, APP development teams may only need to add a few chip design personnel to quickly customize chips based on application scenarios, providing integrated hardware and software solutions.
It is worth mentioning that Leendert van Doorn, Senior Vice President of Qualcomm, also stated that during the transformation process, we increasingly realize that RISC-V needs not just another CPU, but a new paradigm of “platform standards + ecosystem.” Only by completing this mental leap can we quickly integrate the technology stack into vertical tracks such as automotive, industrial, wearables, and XR.
Leendert van Doorn stated that for RISC-V to run “the latest and most important software,” the biggest roadblock is the gap in “basic components + SDKs.”
Historical experience shows that every ISA leap requires “from scratch migration”:
x86-64: From 32-bit to 64-bit, the Windows ecosystem took a full 10 years.
ARM64: Also took 10 years, and it was even more painful than x86-64—there was almost no usable 64-bit Windows ecosystem, so it had to start from scratch.
Therefore, for RISC-V to shorten the “10-year” cycle, it must transform “reinventing the wheel” into “reusable platform migration.”
Thus, simply translating x86 and ARM to RISC-V is far from sufficient.
The new opportunity of the era is open-source, and high performance is the new high ground for RISC-V development. How to form a batch of benchmark products and cultivate an internationally competitive ecosystem is the core issue for all companies at this stage.
04
Conclusion
When the summit calls to avoid confining RISC-V to the positioning of an ARM alternative, it points to a more essential path: the true power of the open instruction set lies in redefining the relationship between chips and scenarios.
If we only heroize based on cost advantages, we will waste the disruptive potential of RISC-V’s customizable architecture for software-hardware synergy.
Of course, the collective awkwardness of IP vendors in the early stages of the ecosystem is unavoidable. How to find a suitable landing application is a question that every vendor must consider at this stage.
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