Latest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom Solutions

1. Overview

The HI3516/9DV500-A0 board is a codec IP motherboard developed for the HiSilicon AI SoC media processing chip, designed to showcase the chip’s powerful multimedia capabilities and peripheral interfaces to customers. It also provides customers with product hardware PCBA based on SoC, opening up the key resources of the chip, allowing for the design of corresponding expansion boards according to various usage scenarios, enriching peripheral interfaces, shortening the development cycle of customer products, and reducing development costs and risks.The module entity diagram is as follows:

The optional CMOS entity diagram is as follows:

Latest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom Solutions

Latest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom Solutions

Latest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom Solutions

2. Main Features of SOC

1) Processor Core

· Dual-core ARM Cortex A55@1000MHz

– 32KB I-Cache, 32KB D-Cache, 256KB L3 cache

– Supports Neon acceleration, integrated FPU processing unit

– Supports TrustZone

2) System Level Acceleration Module

· Integrated hardened standard CRC32/CRC16/CRC8 polynomial operation unit

· Integrated hardened high-speed direct memory access (DMA) module

3) Intelligent Video Analysis

· Neural network supports a complete API and toolchain, easy for customer development

· Upgraded IVE operator, supports feature point detection, perimeter, optical flow, and various computer morphological operators

· Upgraded DPU algorithm implements binocular depth map acceleration unit, maximum resolution 2048 x 2048, maximum disparity 224, processing performance 720p@30fps

4) Video Interface, Encoding

· Supports H.264 BP/MP/HP Level 5.1

· Supports H.265 Main Profile Level 5.1

· H.264/H.265 codec maximum resolution is 6144x 6144, supports I/P frames

· H.264/H.265 multi-stream codec typical performance:

− 3840 x 2160@30fps (encoding) + 1920 x 1080@30fps (encoding) + 720 x 480@30fps (encoding)

− 3840 x 2160@30fps (encoding) + 720 x 480@30fps (encoding) + 1920 x 1080@30fps (decoding)

− 3840 x 2160@30fps (decoding)

· Supports encoding overlay OSD for 8 regions

· Supports various bit rate control modes such as CBR/VBR/AVBR/FIXQP/QPMAP

· Maximum output bitrate of 80Mbps

· Supports video front-end overlay mosaic encoding

· Supports digital watermarking

· Supports PVC perceptual encoding to reduce bitstream

· Supports JPEG Baseline encoding/decoding, JPEG maximum resolution 16384 x 16384, JPEG maximum performance

− Encoding: 3840 x 2160@60fps (YUV420)

− Decoding: 3840 x 2160@30fps (YUV420)

· Supports 8-Lane image sensor serial input, supporting various interfaces such as MIPI/LVDS/Sub-LVDS/HiSPi

· Supports 4-channel sensor input, supports 8/10/12/14 Bit RGB Bayer DC timing video input, maximum clock frequency 148.5MHz

· Supports 1~4 channels of YUV input via MIPI virtual channels

· Supports mainstream CMOS level thermal imaging sensor access

· Supports structured light image modules, supports cw ToF image sensors

3) Security Engine

· Supports TrustZone-based REE/TEE hardware isolation scheme

· Supports neural network model and data protection

· Hardware implementation of AES128/256 symmetric encryption algorithm

· Hardware implementation of RSA3072/4096 signature verification algorithm

· ECC256/384/512 elliptic curve algorithm

· Hardware implementation of SHA256/384/512, HMAC_SHA256/384/512 algorithms

· Hardware implementation of SM2/3/4 national secret algorithms; provides 28Kbit OTP storage space for customer use

4) ISP

· Supports multi-channel sensor simultaneous processing

· Supports 3A (AE/AWB/AF) functions, 3A parameters adjustable by users

· Supports fixed pattern noise (FPN) removal

· Supports bad pixel correction and lens shading correction

· Supports two-frame WDR and Advanced Local Tone Mapping, supports strong light suppression and backlight compensation

· Supports multi-level 3D noise reduction; supports image edge enhancement; supports dehazing; supports dynamic contrast enhancement; supports 3D-LUT color adjustment

· Supports next-generation lens distortion correction

· Supports arbitrary shape geometric correction such as fisheye

· Supports 6-DoF digital stabilization

· Supports gyroscope stabilization and Rolling-Shutter correction

· Supports image Mirror, Flip, 90-degree/270-degree rotation

· Supports real-time DRC, BNR, 3DNR, or DM processing of images using neural networks

· Supports dual light fusion of black and white and color images

5) Peripheral Interfaces

· 1 Gigabit Ethernet interface

− Supports RGMII, RMII interface modes

− Supports acceleration units such as TSO, UFO, COE

· 2 SDIO3.0 interfaces

− SDIO0 supports SDXC cards, maximum capacity 2TB

− SDIO1 supports docking of Wi-Fi modules

· 1 USB3.0/USB2.0 interface, USB Host/Device switchable

· Multiple UART, I2C, SPI, PWM, GPIO interfaces

· Supports one BT.1120 or BT.656 interface output, with BT.1120 maximum performance of 1920×1080@60fps

· Supports 4-Lane Mipi DSI/CSI interface output, maximum 1.8Gbps/lane, performance 3840 x 2160@30fps

· Built-in Audio codec, supports 16bit dual differential voice input and dual single-ended voice output

· Supports multi-protocol voice encoding/decoding, supports audio 3A (AEC/ANR/ALC) processing

· Supports digital interfaces BT.601/BT.656/BT.1120 output ports (supports 8-bit dual data rate)

3. Module Hardware Configuration

3. Module Hardware Configuration

SoC

HI3519/6DV500

Memory

Flash

£ NAND £NOR ReMMC (4bit)

R4GB £8GB £16GB

RAM

RDDR4 £LPDDR4 £LPDDR4X

R2GB £4GB £8GB

Network Interface

8pin wafer 1.25mm socket, supports 100/1000Mbits full/half duplex mode

CMOS Interface

45pin FPC 0.5mm double-row upright connector

Debug Port

8pin wafer 1.25mm socket

Audio, IO Port

6pin wafer 1.25mm socket

Power Port

2pin wafer 1.5mm socket

Expansion Port

36pin FPC 0.5mm double-row upright connector (USB3.0, I/O, UART, SDIO3.0)

RTC

RBuilt-in RTC £External RTC

Firmware Encryption

RSupported £Not Supported

Watchdog

RBuilt-in £External

Board Size

42*42mm

Operating Temperature

-25℃ (non-condensing) ~ 60℃

Operating Voltage

12V±20 @ 1A

Basic Protection

EFT : ±1kV/5KHz surge:±0.5kV @ 1.2/50us (DM)

4. 2D Structure Diagram and Interface Description

Latest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom SolutionsLatest HiSilicon Platform HI3519/Hi3516DV500 Codec IP Motherboard/Custom Solutions

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