01
Current Status of Automotive SoC Chips
The first application of SoC in automobiles was in the smart cockpit. With the development of smart cockpits, not only is powerful CPU computing required to enhance task processing capabilities, but also strong GPU computing to handle video, images, and other unstructured data, efficient AI computing to meet the intelligent interaction experience requirements of smart cockpits, and high-speed DSP computing to achieve high-bandwidth real-time communication. Additionally, it must be able to operate systems compatible with mobile ecosystems to quickly enhance entertainment experiences. In summary, the demand for smart cockpits in typical application scenarios such as 4G communication, in-car Wi-Fi, cockpit gesture recognition, high-quality audio and video processing, coding and decoding, and image stitching is highly compatible with the business scenarios of smartphones. Therefore, leveraging its technological strength and brand advantages in consumer electronics and communications, Qualcomm developed the automotive-grade SoC chip Snapdragon 620A based on the Snapdragon 600 platform in 2014, achieving great success. As of now, Qualcomm’s smart cockpit SoC chips have evolved to the fourth generation SA8295.
In the field of intelligent driving, processing massive frame images puts a significant strain on the chip’s parallel computing capabilities. Clearly, CPUs, which excel in logic and digital computation, cannot meet the demands of numerous parallel simple computation tasks. Therefore, integrated SoC chips with CPU and XPU (GPU/NPU/TPU) are typically used in autonomous driving. As the level of intelligent driving advances, the computing power of intelligent driving SoCs is also continuously improving. Currently, the highest AI computing power mass-produced in intelligent driving SoCs is NVIDIA’s Orin.
Since the scenarios for smart cockpits and intelligent driving differ, the focus of computing power also varies, so SoCs for smart cockpits and intelligent driving will develop parallelly for a long time.
This September, Qualcomm and NVIDIA almost simultaneously released their automotive supercomputing chips, Thor (NVIDIA) and Snapdragon Ride Flex (Qualcomm), both of which can support functions for smart cockpits and intelligent driving. The industry couldn’t help but exclaim whether the era of integrated cockpit and driving chips is about to arrive. In this regard, I believe that truly achieving cockpit-driving integration still has a long way to go.
First, the functional safety levels of smart cockpits and intelligent driving differ, and how to create an OS that accommodates different functional safety levels is a challenge.
Second, true cockpit-driving integration requires flexible allocation of computing power, whereas Thor currently uses static configuration, and once computing power is allocated, it cannot switch based on scenarios.
Third, many automotive companies have their smart cockpit and intelligent driving departments separated, and how to coordinate collaboration within a single chip is also a challenge, as there are no mature experiences to follow.
Therefore, for some time to come, having separate SoCs for smart cockpits and intelligent driving will remain the mainstream solution.
In fact, whether it is cockpit-driving integration or maintaining independent development of smart cockpits and intelligent driving, to understand the future development direction of automotive SoCs, one must first answer a question: What determines the development direction of automotive SoC chips?
02
Challenges of Automotive Intelligence
Cao Sir believes that the development direction of automotive SoC chips is determined by the development of the vehicle’s electronic and electrical architecture!
The electronic and electrical architecture was first proposed by Delphi, integrating the design principles of automotive electronic and electrical systems, central electrical box design, connector design, electronic and electrical distribution systems, etc., into a comprehensive vehicle electronic and electrical solution. According to the widely accepted Bosch definition in the industry, electronic and electrical architecture is divided into three major stages: distributed architecture, domain-centralized architecture, and central centralized architecture. In recent years, with the rapid development of the automotive “new four modernizations,” many automakers have transitioned from distributed electrical architecture to domain-centralized electrical architecture, with some even leapfrogging to central centralized electrical architecture, showing a rapid evolution of electronic and electrical architecture overall. The reasons behind this are that the automotive industry is facing four major challenges: “Weight reduction and cost reduction,” “Intelligent networking,” “Rapid iteration,” and “Business model disruption.”
1. “Weight reduction and cost reduction” challenge, as the number of intelligent functions in cars increases, traditional distributed architecture leads to a high number of controllers, resulting in high costs and weight. Statistics show that a high-end car based on traditional distributed electronic and electrical architecture has as many as 70 controllers, with the entire electrical system weighing 80Kg.
2. “Intelligent networking” challenge, in the wave of new four modernizations, an intelligent connected car collects at least 10TB of data daily, requiring higher standards for internal vehicle communications and communications between the vehicle and the outside world. Traditional electronic and electrical architectures based mainly on CAN communications cannot meet these requirements.
3. “Rapid iteration” challenge, traditional low cohesion and high coupling electrical architecture has poor reusability and scalability, with long development cycles and high costs. The future market is one where fast fish eat slow fish; traditional distributed electronic and electrical architecture is low cohesion and high coupling, requiring many controllers to cooperate to add a new intelligent function, which is not only costly but also time-consuming.
4. “Business model disruption” challenge, the previous profit model of selling cars + after-sales has shifted to an internet-based “subscription” profit model, and traditional signal-oriented electrical architecture clearly cannot support this “subscription” model, leading to the emergence of service-oriented SOA electrical architecture.
03
Development Direction of Automotive SoC Chips
To meet the above four challenges, the future new electronic architecture must possess “low power consumption,” “reliable and trustworthy,” “high integration,” “reusable,” “scalable,” “high performance,” “low coupling,” and “high openness” as its eight core characteristics. Among these, “high performance,” “low power consumption,” “high integration,” and “reliable and trustworthy” determine the development direction of automotive SoC chips.
Due to multi-screen interconnection, smart interaction, intelligent driving, and other scenario-based functions having extremely high requirements for chip performance. In recent years, the CPU computing power of smart cockpit chips has significantly improved, increasing from several KDMIPS to over 100 KDMIPS in less than 7 years. With the development of autonomous driving, the AI computing power of intelligent driving chips has also greatly increased. Industry standards suggest that achieving L2-level autonomous driving assistance requires computing power below 10 TOPS, L3-level requires 30-60 TOPS, L4-level requires over 300 TOPS, and L5-level requires over 1000 TOPS, even exceeding 4000+ TOPS.
“Low Power Consumption”
Preliminary estimates suggest that for a new energy vehicle under CLTC conditions, every increase of 50w in power consumption results in a loss of 8-10Km in range. Therefore, the new electronic architecture imposes higher demands on chip energy efficiency. Reducing power consumption requires not only improvements in process nodes but also transitioning from general-purpose chips to specialized ASIC chips tailored for specific algorithms. Currently, autonomous driving chips use a GPU + FPGA solution. In the future, once the algorithms stabilize, ASIC will become mainstream. Currently, the energy efficiency ratio of mainstream products has evolved from the initial 0.8TOPS/W (EyeQ4), 1TOPS/W (Xavier) to 4.44TOPS/W (NVIDIA Orin), 4.8TOPS/W (Horizon Journey 5), with future mainstream products expected to have a power consumption of at least 6TOPS/W.
“High Integration”
The automotive electronic and electrical architecture (E/E architecture) is gradually evolving from traditional distributed to centralized. In a centralized E/E architecture, new domain controllers integrate more functions, and the main control chip must enhance its computing power and performance accordingly. Under this trend, automotive chips are transitioning from general-purpose, decentralized single-function chips (MCUs) to customized, integrated multifunction SoC (System on Chip) chips. SoC is a system-level chip that integrates key system components onto a single chip, enhancing performance while effectively reducing the development cost and cycle of system products, thus improving product competitiveness. In the future, under centralized electrical architecture, there is a trend for smart cockpit SoCs and intelligent driving SoCs to merge.
“Reliable and Trustworthy”
As the requirements for functional safety and cybersecurity continue to rise, the reliability and trustworthiness of SoC chips become paramount. The realization of reliability technology is fundamentally based on fault tolerance, which mainly relies on resource redundancy and the organization of system reconstruction resources. Redundancy includes hardware redundancy, software redundancy, time redundancy, and information redundancy. Hardware redundancy adds additional backup hardware beyond conventional hardware function design, allowing the system to continue functioning normally when conventional hardware fails; software redundancy adds extra programs for error detection and correction, enabling programs to self-correct when errors occur; time redundancy allocates extra time for a specific instruction or program to repeat execution; information redundancy increases the redundancy of information, allowing it to possess self-detection and correction capabilities.
04
How Can Domestic SoCs Break Through?
In the short term, leveraging first-mover advantages, the scale of networks, and iteration speed, Qualcomm and NVIDIA remain unmatched in the smart cockpit and intelligent driving fields. How can domestic SoCs break through in a competitive landscape with strong rivals and compete on the same stage with them?
First, it is essential to focus on user needs and build an innovative management process. Taking autonomous driving AI chips as an example, many chip companies currently develop IP based on their algorithms. Users buying their chips must also use their algorithms. Some chip products even cannot support CNN + Transformer algorithms, while others continuously track state-of-the-art visual learning algorithms, ensuring compatibility during the design process. Additionally, they provide hardware-software co-design and toolchain support for customers to build their own algorithm IP, thus creating a more efficient intelligent driving SoC tailored for customers.
Second, it is crucial to build a high-level technical team. The chip industry is a systemic engineering field with very high and broad requirements for specialized disciplines, including but not limited to mathematics, chemistry, physics, imaging, optics, etc. The complexity and breadth of this field test engineers’ solid theoretical foundations and outstanding engineering implementation capabilities! Therefore, a reasonable division of work and high-quality talent are the essential soul of chip design companies and the foundation for building the capability for positive chip development.
Third, for smart cockpit chips, with the landing of a series of intelligent cockpit scenarios such as the in-car metaverse and non-touch interaction, the trend of smart cockpit SoC computing power development is aligning with that of PCs. The mainstream cockpit chips in the current market will be replaced by higher computing power SoCs, and during this transition, smart cockpit SoC chips pursuing extreme computing power will gain market favor.
Fourth, for intelligent driving AI chips, as computing power continues to increase, it significantly raises power consumption, cost, and area. Thus, solely relying on chip computing power stacking cannot solve the support issues for intelligent driving system computing platforms. I believe that the infinite expansion of computing power will not be the future trend; compared to computing power exceeding a thousand TOPS, precise and efficient AI computing power and better software training are more important, saving development cycles and costs for automotive enterprises.
Charles Dickens once said in “A Tale of Two Cities”: “It was the best of times, it was the worst of times.” In the process of reforming the new electronic and electrical architecture, the automotive SoC market landscape will undergo profound changes. It is still too early to conclude who will dominate the future, but I believe that chip companies centered around user needs and deeply engaged in technology will have more opportunities!
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