H20 Chip and RTX Pro GPU
Image source: NVIDIA official website
Current Events
Recently, NVIDIA CEO Jensen Huang visited China and brought two significant announcements: NVIDIA has been approved to sell the H20 chip in China and has launched a new product, the RTX Pro GPU, aimed at the Chinese market. Following the announcement, it immediately sparked heated discussions in the domestic tech community, and the stock market responded positively.
So, as the H20 chip is a product balancing policy compliance and market demand, what technical dimensions does it precisely target? What new developments are behind the newly launched RTX Pro GPU concerning digital twin technology? This article will track the cutting-edge technologies behind these two highly anticipated products through the IEEE Xplore literature database.
Image source: NVIDIA official website
Using the IEEE Xplore Platform
Tracking Chip Technology Research Trends
Compute Density
Compute density refers to the computational power a chip can provide per unit area or per unit power consumption, which is a core metric for measuring chip efficiency. The higher the compute density, the faster the AI task processing speed at the same size. The half-precision compute power of the H20 chip is approximately 296 TFLOPS, which is only about 15% of the H100 chip (1979 TFLOPS).
In the IEEE Xplore digital library, to search for research related to Compute Density, please refer to the following content.
Scan the QR code below to learn about related technical literature.
Interconnect Bandwidth
Interconnect bandwidth reflects the speed of data exchange between multiple chips/cards, determining the scalability of distributed computing. High interconnect bandwidth can reduce communication latency during multi-GPU collaborative training. The NVLink interconnect bandwidth of the H20 has been halved from 900 GB/s of the H100 to 400 GB/s.
In the IEEE Xplore digital library, to search for research related to Interconnect Bandwidth, please refer to the following content.
Scan the QR code below to learn about related technical literature.
Memory Bandwidth
Memory bandwidth refers to the data transfer rate between GPU memory and computing cores, affecting the data throughput efficiency of large models. The higher the bandwidth, the more it can alleviate the “memory wall” bottleneck in AI tasks. The memory bandwidth of the H20 chip is 4.0 TB/s, slightly lower than the H100 chip’s 4.8 TB/s.
In the IEEE Xplore digital library, to search for research related to Memory Bandwidth, please refer to the following content.
Scan the QR code below to learn about related technical literature.
Using the IEEE Xplore Platform
Tracking Digital Twin Technology Research Trends
Digital Twin Technology
Digital twin technology creates a real-time mapping of physical entities (such as factories, cities, or chips) through virtual models, enabling data-driven simulation and monitoring. Jensen Huang stated in a media interview that the new product RTX Pro is specifically designed for digital twin applications, which are crucial in fields such as digital factories, smart factories, and robotics.
In the IEEE Xplore digital library, to search for research related to Digital Twin, please refer to the following content.
Scan the QR code below to learn about related technical literature.
NVIDIA’s Publication Status in IEEE
In the IEEE Xplore platform, search for NVIDIA‘s publication status.
Scan the QR code below to learn about NVIDIA’s related publications. You can also explore NVIDIA’s R&D trends through a user-friendly search interface. For more insights, please contact [email protected].
ISSCC Short Courses & Tutorials Collection
After learning about NVIDIA’s chip technologies, do you also want to systematically master cutting-edge technologies in AI and chips? Then don’t miss the upcoming introduction of the ISSCC Short Courses & Tutorials Collection~
ISSCC (International Solid-State Circuits Conference) is the premier academic conference in the field of integrated circuit design, often referred to as the “Olympics of Chip Design”. It is organized by the IEEE Solid-State Circuits Society and has been held annually since 1953, showcasing the latest research achievements in solid-state circuits and system-on-chip (SoC) for over 70 years, serving as the primary international academic platform.
Every year, ISSCC offers a series of Short Courses and Tutorials, which are crafted by authoritative experts in the field. These contents will be released as a collection, focusing on cutting-edge technology directions such as wireless communication, artificial intelligence, and circuit systems, providing systematic and in-depth study materials. After subscribing, users can access over 200 video resources, including premium courses and tutorial recordings from 2011 to the present.
For more information, please click the end of the article “Read the original text” to get the course details page. The editor has also prepared special issues on top semiconductor conferences and reviews of popular ISSCC articles.
To apply for free access to IEEE technical literature, please contact the IEEE database team. (Email: [email protected])
“IEEEXplore Microservices” is operated by iGroup China, a partner of IEEE. iGroup China represents IEEE, ACS, APS, and other internationally renowned academic institutions, providing localized support and services to over 1,000 higher education institutions and more than 100 large enterprises in China.