In the design of embedded systems using MCU, when the program or data memory is too large to fit into on-chip flash or SRAM, developers often consider using SDRAM.
Don’t ask me why your MCU doesn’t support SDRAM
SDRAM stands for Synchronous Dynamic Random Access Memory. In microcontroller applications, the microcontroller accesses SDRAM using an external memory controller (EMC), and the SDRAM clock frequency is typically 100MHz or 133MHz.
The external memory controller usually does not support DDR SDRAM, and data is sampled only on the rising edge, meaning the parallel data bus can accept a command and transfer one data word per clock cycle.
Executing programs in SDRAM is a typical use case for SDRAM, and here we will introduce the methods for executing programs in SDRAM and the performance benchmarks of executing programs in SDRAM.
SDRAM Initialization
SDRAM must be configured before use, and the initialization of SDRAM consists of 6 steps.
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Configure the SDRAM clock frequency, byte order, and timing parameters in the EMC registers. The timing for SDRAM is quite complex, and users need to refer to the relevant SDRAM chip manual for timing parameters (such as refresh cycle, precharge command cycle, self-refresh exit time, write recovery time, etc.).
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Send NOP command
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Send precharge command
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Send auto-refresh command twice
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Set SDRAM mode
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Send normal operation command
At system startup, SDRAM has not been initialized. In theory, SDRAM initialization can occur at any time after system startup. However, due to the complexity of the SDRAM initialization process and the resources it consumes, SDRAM initialization must occur after the required system resources have been initialized.
Specifically, developers need to pay attention to the following details when initializing SDRAM right after the chip starts (e.g., in Reset_Handler):
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Since the SDRAM initialization function uses the system stack or global variables, developers must ensure that the physical memory where the system stack or global variables reside is powered on and clock enabled in time.
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Before the program jumps to the main program, if the global variables are not zeroed or initialized, and SDRAM initialization is executed before the main function, developers must manually initialize the variables.
For example, in LPC5460x, developers need to initialize SDRAM in the SystemInit function, which is called by Reset_Handler. Before calling the system initialization, the SRAM clock must be enabled by setting the AHBCLKCTRLSET0 register.
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
; clock control SRAM1/SRAM2/SRAM3 for stack
LDR r0, = 0x40000220 ; AHBCLKCTRLSET0
MOV r1, #0x38
STR r1, [r0]
LDR r0, =SystemInit
BLX r0
LDR r0, =__main
BX r0
ENDP
SDRAM Memory Layout
When using SDRAM, the external memory controller (EMC) allocates a certain address space for SDRAM. Developers can use linker description files to allocate code or data to SDRAM. It is worth noting that linker script programming varies between different IDEs.
Taking the LPC5460x series microcontroller as an example, SDRAM supports 4 chip select areas, each supporting a maximum of 256MB space.
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When the hardware connection of SDRAM uses chip select 0, the steps to copy the Coremark benchmark program loaded in SPI FLASH to SDRAM for execution on the KEIL platform are as follows. (The coremark benchmark program includes core_list_join.c, core_matrix.c, core_state.c, and core_util.c).
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Define the SDRAM region, starting at 0xA0000000, with a size of 0x80000. Define the SPI FLASH region, with a size of 0x80000 (the starting address of SPI FLASH memory is 0x10000000).
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Use the “SDRAM_Data” and “SDRAM_Function” attributes in the C source code to mark data or programs located in the SDRAM region. (SDRAM_Data and SDRAM_Function are just text names).
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It is also possible to configure the entire data and program segments of the target file to SDRAM.
#define m_spifi_start 0x10000000
#define m_spifi_size 0x800000
#define m_sdram_start 0xA0000000
#define m_sdram_size 0x80000
LR_m_text2 m_spifi_start m_spifi_size { ; load to SPIFI
LR_m_sdram_text m_sdram_start m_sdram_size {
*(SDRAM_Data) *(SDRAM_Function) core_list_join.o core_matrix.o core_state.o
core_util.o
}
Configuring MPU
When running programs in SDRAM, developers may need to configure the ARM Cortex-M memory protection unit (MPU).
The memory protection unit (MPU) is a programmable unit used to define memory access permissions. When the MPU is not enabled, the memory address space has default access permissions.
As described in the ARM Cortex™-M4 Device Generic User Guide, when a program executes code in SDRAM and the default attribute of the SDRAM memory-mapped address is set to disallow execution, the core will generate a HARDFAULT exception, and the instruction access violation flag SCB->CFSR will be set to 1. This exception indicates that the processor attempted to fetch instructions from a location where execution is not permitted.
Therefore, when SDRAM is mapped to a default non-executable address space (e.g., in LPC5460x, SDRAM is mapped to the starting address of 0xA0000000), developers must configure and enable the MPU to execute code in SDRAM. In the example below, the code configures and enables the MPU, allowing execution from the memory region ranging from 0xA0000000 to 0xA0100000.
MPU->RNR = 0; //Region number 0
MPU->RBAR = 0xA0000000; //Region base address
/* Full Access | TEX: 000 | S: 0 | C: 0 | B:0 (No cacheable, no shareable)| 1M SIZE | ENABLE */
MPU->RASR = (0 << 28) | (0x3 << 24) | (0x0 << 19) | (0 << 18) | (0 << 17) | (0 << 16) | (0xFF < 8) | (0x13 << 1) | (1 << 0); //Region size and enableMPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
SDRAM Performance Benchmark
Finally, after running the CoreMark performance benchmark on the LPC5460x, I summarized a few experiences to share with everyone.
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The code execution efficiency in SDRAM (16-bit bandwidth) is only 40% of the efficiency performance when executed in internal SRAM, and about 50% of the performance when running code in internal FLASH;
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When code runs in SDRAM, a higher CPU frequency (without Cache) does not improve execution efficiency, as SDRAM bandwidth becomes the bottleneck of system performance.
Based on these test results, it is recommended that when higher performance is required, program code should be executed in internal SRAM, while large-capacity external SDRAM should be used to store massive data.
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