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HLS

HLS materials are relatively scarce. Currently, apart from the official white paper (the best material), there is no detailed introduction on this aspect in China. However, today I saw that Teacher He Bin has published a book, which is the one below:

Looking at the publication date:

Author: He Bin, Zhang Yanhui

Publication Date: 2019-01

It is still fresh. Those interested can buy a physical book to learn, mine is still on the way…

Here are a few tutorials on HLS design, including official materials:

Mi Lian’s tutorial on HLS in image processing:

Link: https://pan.baidu.com/s/1I15igy9iCaCwikZCkWwoVQ

Extraction Code: 2bhj

Source code for the above tutorial:

Link: https://pan.baidu.com/s/1I15igy9iCaCwikZCkWwoVQ

Extraction Code: 2bhj

Official materials:

Link: https://pan.baidu.com/s/1kblxn4Tq1XabglaxEHDDGA

Extraction Code: itjj

Xilinx FPGA Digital Signal Processing Guide: From HDL to Model and C Description

Link: https://pan.baidu.com/s/1on7iZhxBVTrz-1idEAqznQ

Extraction Code: kstq

FPGA Design Guide: Devices, Tools, and Processes

This book helps you better understand the internal workings of FPGA:

Link: https://pan.baidu.com/s/1vQnsinASz0gRDSdGe4J3jg

Extraction Code: rxgs

This book introduces what FPGA is, how FPGA works, how to program FPGA, and various concepts, devices, and tools encountered in FPGA design. The book presents what FPGA is, how FPGA works, how to program FPGA, and various concepts, devices, and tools encountered in FPGA design, such as traditional HDL/RTL-based simulation and logic synthesis, the latest pure C/C++ design capture and synthesis techniques, and DSP-based design processes. Additionally, the book covers a wealth of technical details required by engineers. This book is suitable for engineers designing with FPGA, software engineers developing embedded application tasks, and students and teachers in electrical engineering majors at higher education institutions.

Author Profile

Clive “Max” Maxfield, a well-known expert in the global semiconductor design field, is the editor-in-chief of the FPGA professional website Programmable Logic DesignLine. Mr. Maxfield has extensive experience in circuit design and development and is renowned worldwide for his outstanding writing skills. He has long contributed columns to top magazines and websites such as EDN and EE Design and has written several bestselling books on electronic technology.

Table of Contents

Chapter 1 Introduction

1.1 What is FPGA

1.2 Why FPGA is Interesting

1.3 Uses of FPGA

1.4 Content of This Book

1.5 What This Book Does Not Include

1.6 Target Audience

Chapter 2 Basic Concepts

2.1 Core of FPGA

2.2 Simple Programmable Functions

2.3 Fuse Connection Technology

2.4 Anti-Fuse Technology

2.5 Mask Programmable Devices

2.6 PROM

2.7 EPROM-based Technology

2.8 EEPROM-based Technology

2.9 Flash-based Technology

2.10 SRAM-based Technology

2.11 Summary

Chapter 3 Origins of FPGA

3.1 Related Technologies

3.2 Transistors

3.3 Integrated Circuits

3.4 SRAM/DRAM and Microprocessors

3.5 SPLD and CPLD

3.5.1 PROM

3.5.2 PLA

3.5.3 PAL and GAL

3.5.4 Other Programmable Options

3.5.5 CPLD

3.5.6 ABEL, CUPL, PALASM, JEDEC, etc.

3.6 Application-Specific Integrated Circuits (Gate Arrays, etc.)

3.6.1 Full Custom

3.6.2 Micromatrix and Micromosaic

3.6.3 Gate Arrays

3.6.4 Standard Cell Devices

3.6.5 Structured ASIC

3.7 FPGA

3.7.1 FPGA Platforms

3.7.2 FPGA-ASIC Hybrid

3.7.3 How FPGA Manufacturers Design Chips

Chapter 4 Comparison of FPGA Architectures

4.1 A Reminder

4.2 Some Background Information

4.3 Anti-Fuse vs. SRAM and Others

4.3.1 SRAM-based Devices

4.3.2 Security Issues and Solutions for SRAM-based Devices

4.3.3 Anti-Fuse-based Devices

4.3.4 EPROM-based Devices

4.3.5 EEPROM/FLASH-based Devices

4.3.6 FLASH-SRAM Hybrid Devices

4.3.7 Summary

4.4 Fine, Medium, and Coarse-Grained Architectures

4.5 MUX and LUT-based Logic Blocks

4.5.1 MUX-based Structures

4.5.2 LUT-based Structures

4.5.3 MUX vs. LUT

4.5.4 3, 4, 5, or 6 Input LUT

4.5.5 LUT vs. Distributed RAM and SR

4.6 CLB, LAB, and Slices

4.6.1 Xilinx Logic Units

4.6.2 Altera Logic Components

4.6.3 Slicing and Dicing

4.6.4 CLB and LAB

4.6.5 Distributed RAM and Shift Registers

4.7 Fast Carry Chains

4.8 Embedded RAM

4.9 Embedded Multipliers, Adders, MACs, etc.

4.10 Embedded Processor Cores (Hard and Soft)

4.10.1 Hard Microprocessor Cores

4.10.2 Soft Microprocessor Cores

4.11 Clock Trees and Timing Managers

4.11.1 Clock Trees

4.11.2 Clock Managers

4.12 General I/O

4.12.1 Configurable I/O Standards

4.12.2 Configurable I/O Impedance

4.12.3 Core and I/O Voltage

4.13 Gigabit Transmission

4.14 Hard IP, Soft IP, and Firm IP

4.15 System Gates vs. Actual Gates

4.16 FPGA Year

Chapter 5 FPGA Programming (Configuration)

5.1 Introduction

5.2 Configuration Files

5.3 Configuration Units

5.4 Anti-Fuse-based FPGAs

5.5 SRAM-based FPGAs

5.5.1 The Quick Process Deceives the Eye

5.5.2 Programming Embedded (Block) RAM, Distributed RAM

5.5.3 Multi-Programming Chains

5.5.4 Quick Reinitialization of Devices

5.6 Using Configuration Ports

5.6.1 FPGA as Master Device for Serial Download

5.6.2 FPGA as Master Device for Parallel Download

5.6.3 FPGA as Slave Device for Parallel Download

5.6.4 FPGA as Slave Device for Serial Download

5.7 Using JTAG Ports

5.8 Using Embedded Processors

Chapter 6 Who is Involved in the Game

6.1 Introduction

6.2 FPGA and FPAA Providers

6.3 FPNA Providers

6.4 Full Line EDA Providers

6.5 Specialized FPGA and Independent EDA Providers

6.6 FPGA Design Consultants Using Specialized Tools

6.7 Open Source, Free, and Low-Cost Design Tools

Chapter 7 FPGA vs. ASIC Design Styles

7.1 Introduction

7.2 Coding Styles

7.3 Pipelining and Logic Levels

7.3.1 What is Pipelining

7.3.2 Pipelining in Electronic Systems

7.3.3 Logic Levels

7.4 Asynchronous Design Practices

7.4.1 Asynchronous Structures

7.4.2 Combinational Circuits

7.4.3 Delay Chains

7.5 Clock Considerations

7.5.1 Clock Domains

7.5.2 Clock Balancing

7.5.3 Gated Clocks and Enabled Clocks

7.5.4 PLL and Clock Adjustment Circuits

7.5.5 Reliability of Data Transfer Across Clock Domains

7.6 Register and Latch Considerations

7.6.1 Latches

7.6.2 Flip-Flops with Set and Reset Inputs

7.6.3 Global Reset and Initialization Conditions

7.7 Resource Sharing (Time Division Multiplexing)

7.7.1 Use It or Lose It

7.7.2 Other Content

7.8 State Machine Coding

7.9 Testing Methodology

Chapter 8 Schematic-Based Design Flow

8.1 The Good Old Days

8.2 Early EDA

8.2.1 Front-End Tools, Such as Logic Simulation

8.2.2 Back-End Tools, Such as Layout Design

8.2.3 CAE + CAD = EDA

8.3 Simple Schematic-Driven ASIC Design Flow

8.4 Simple (Early) Schematic-Driven FPGA Design Flow

8.4.1 Mapping

8.4.2 Packaging

8.4.3 Layout and Routing

8.4.4 Timing Analysis and Post-Layout Simulation

8.5 Flat Schematics vs. Hierarchical Schematics

8.5.1 Dull Flat Schematics

8.5.2 Hierarchical (Module-Based) Schematics

8.6 Today’s Schematic-Driven Design Flow

Chapter 9 HDL-Based Design Flow

9.1 Problems with Schematic-Based Flow

9.2 Emergence of HDL-Based Design Flow

9.2.1 Different Levels of Abstraction

9.2.2 Early HDL-Based ASIC Design Flow

9.2.3 Early HDL-Based FPGA Design Flow

9.2.4 FPGA Flow with Known Structure

9.2.5 Logic Synthesis vs. Physical Synthesis

9.3 Life of Graphical Design Input

9.4 Absolute Surplus of HDL

9.4.1 Verilog HDL

9.4.2 VHDL and VITAL

9.4.3 Mixed-Language Design

9.4.4 UDL/I

9.4.5 Superlog and SystemVerilog

9.4.6 SystemC

9.5 Worth Considering

9.5.1 Worrying, Very Worrying

9.5.2 Serial vs. Parallel Multiplexers

9.5.3 Caution with Latches

9.5.4 Smart Use of Constants

9.5.5 Resource Sharing Considerations

9.5.6 Other Content Not to Be Ignored

Chapter 10 Silicon Virtual Prototypes in FPGA Design

10.1 What is a Silicon Virtual Prototype

10.2 ASIC-based SVP Methods

10.2.1 Gate-Level SVP (Generated by Fast Synthesis)

10.2.2 Gate-Level SVP (Generated by Gain-Based Synthesis)

10.2.3 Cluster SVP

10.2.4 RTL-Based SVP

10.3 FPGA-Based SVP

10.3.1 Interactive Operation

10.3.2 Incremental Layout and Routing

10.3.3 RTL-Based FPGA SVP

Chapter 11 C/C++ Based Design Flow

11.1 Problems with Traditional HDL Design Flow

11.2 C vs. C++ and Parallel Execution vs. Sequential Execution

11.3 SystemC Based Design Flow

11.3.1 What is SystemC and Where Does It Come From

11.3.2 SystemC 1.0

11.3.3 SystemC 2.0

11.3.4 Levels of Abstraction

11.3.5 Optional SystemC Based Design Flow

11.3.6 Love It or Hate It

11.4 Enhanced C/C++ Based Design Flow

11.4.1 What is Enhanced C/C++

11.4.2 Optional Enhanced C/C++ Design Flow

11.5 Pure C/C++ Based Design Flow

11.6 Different Levels of Abstraction for Synthesis

11.7 Mixed Language Design and Verification Environment

Chapter 12 DSP-Based Design Flow

12.1 Introduction to DSP

12.2 Optional DSP Implementation Solutions

12.2.1 Choose Any Device, But Don’t Let Me See Which One

12.2.2 System-Level Evaluation and Algorithm Verification

12.2.3 Software Running in DSP Cores

12.2.4 Dedicated DSP Hardware

12.2.5 FPGA Resources Related to DSP

12.3 FPGA-Centric Design Flow for DSP

12.3.1 Domain-Specific Languages

12.3.2 System-Level Design and Simulation Environment

12.3.3 Floating Point vs. Fixed Point Representation

12.3.4 System/Algorithm Level to RTL Conversion (Manual)

12.3.5 System/Algorithm Level to RTL Conversion (Automatic)

12.3.6 System/Algorithm Level to C/C++ Conversion

12.3.7 Module-Level IP Environment

12.3.8 Don’t Forget the Test Platform

12.4 DSP and VHDL/Verilog Mixed Design Environment

Chapter 13 Embedded Processor-Based Design Flow

13.1 Introduction

13.2 Hard Cores vs. Soft Cores

13.2.1 Hard Cores

13.2.2 Microprocessor Soft Cores

13.3 Dividing Design into Hardware and Software Parts

13.4 Worldview of Hardware and Software

13.5 Using FPGA as Its Own Development Environment

13.6 Enhancing Design Visibility

13.7 Other Mixed Verification Methods

13.7.1 RTL (VHDL or Verilog)

13.7.2 C/C++, SystemC, etc.

13.7.3 Physical Chips in Hardware Simulators

13.7.4 Instruction Set Simulators

13.8 A Quite Clever Design Environment

Chapter 14 Modular Design and Incremental Design

14.1 Treating Design as a Large Module

14.2 Dividing Design into Smaller Modules

14.2.1 Modular Design

14.2.2 Incremental Design

14.2.3 Issues That Exist

14.3 There Are Always Other Ways

Chapter 15 High-Speed Design and Other PCB Design Considerations

15.1 Before You Start

15.2 We Are All Young, So

15.3 An Era of Change

15.4 Other Considerations

15.4.1 High-Speed Design

15.4.2 Signal Integrity Analysis

15.4.3 SPICE and IBIS

15.4.4 Startup Power

15.4.5 Using Internal Termination Resistance

15.4.6 Serial or Parallel Data Processing

Chapter 16 Observing FPGA Internal Nodes

16.1 Lack of Visibility

16.2 Using Multiplexing Techniques

16.3 Dedicated Debugging Circuits

16.4 Virtual Logic Analyzers

16.5 Virtual Lines

16.5.1 Problem Description

16.5.2 Virtual Line Solutions

Chapter 17 IP

17.1 Sources of IP

17.2 Manually Optimized IP

17.2.1 Unencrypted RTL-level IP

17.2.2 Encrypted RTL-level IP

17.2.3 Netlist-level IP Before Layout and Routing

17.2.4 Netlist-level IP After Layout and Routing

17.3 IP Core Generators

17.4 Synthesis Materials

Chapter 18 Porting Between ASIC Design and FPGA Design

18.1 Alternative Design Methods

18.1.1 Only Doing FPGA Design

18.1.2 Conversions Between FPGAs

18.1.3 Conversion from FPGA to ASIC

18.1.4 Conversion from ASIC to FPGA

Chapter 19 Design Tools for Simulation, Synthesis, Verification, etc.

19.1 Introduction

19.2 Simulation (Cycle-Based, Event-Driven, etc.)

19.2.1 What is an Event-Driven Logic Simulator

19.2.2 Brief History of Event-Driven Logic Simulators

19.2.3 Logic Values and Different Logic Value Systems

19.2.4 Mixed Language Simulation

19.2.5 Other Delay Formats

19.2.6 Cycle-Based Simulators

19.2.7 Choosing the Best Logic Simulator in the World

19.3 Synthesis (Logic/HDL Synthesis and Physical Synthesis)

19.3.1 Logic/HDL Synthesis Techniques

19.3.2 Physical Synthesis Techniques

19.3.3 Timing Re-timing, Duplication, and Secondary Synthesis

19.3.4 Choosing the Best Synthesis Tool in the World

19.4 Timing Analysis (Static and Dynamic)

19.4.1 Static Timing Analysis

19.4.2 Statistical Static Timing Analysis

19.4.3 Dynamic Timing Analysis

19.5 General Verification

19.5.1 Verifying IP

19.5.2 Verification Environment and Creating Testbench

19.5.3 Analyzing Simulation Results

19.6 Formal Verification

19.6.1 Different Types of Formal Verification

19.6.2 What Exactly is Formal Verification

19.6.3 Terminology and Definitions

19.6.4 Other Optional Assertion/Property Specification Techniques

19.6.5 Static Formal Verification vs. Dynamic Formal Verification

19.6.6 Summary of Various Languages

19.7 Mixed Design

19.7.1 HDL Language to C Language Conversion

19.7.2 Code Coverage

19.7.3 Performance Analysis

Chapter 20 Choosing the Right Device

20.1 A Rich Selection

20.2 It Would Be Nice to Have a Selection Tool

20.3 Process

20.4 Basic Resources and Packaging

20.5 General I/O Interfaces

20.6 Embedded Multipliers, RAM, etc.

20.7 Embedded Processor Cores

20.8 Gigabit I/O Capability

20.9 Available IP

20.10 Speed Grades

20.11 Easy Annotation

Chapter 21 Gigabit Transceivers

21.1 Introduction

21.2 Differential Pairs

21.3 Various Standards

21.4 8bit/10bit Encoding, etc.

21.5 Deep Inside Transceiver Modules

21.6 Combining Multiple Transceivers

21.7 Configurable Resources

21.7.1 Comma Detection

21.7.2 Differential Output Swing

21.7.3 On-Chip Termination Resistance

21.7.4 Pre-emphasis

21.7.5 Equalization

21.8 Clock Recovery, Jitter, and Eye Diagrams

21.8.1 Clock Recovery

21.8.2 Jitter and Eye Diagrams

Chapter 22 Reconfigurable Computing

22.1 Dynamically Reconfigurable Logic

22.2 Dynamically Reconfigurable Interconnects

22.3 Reconfigurable Computing

Chapter 23 Field Programmable Node Arrays

23.1 Introduction

23.2 Algorithm Evaluation

23.3 picoChip’s picoArray Technology

23.3.1 An Ideal picoArray Application: Wireless Base Stations

23.3.2 picoArray Design Environment

23.4 QuickSilver’s ACM Technology

23.4.1 Designing Mixed Nodes

23.4.2 System Controller Nodes, Input/Output Nodes, and Other Nodes

23.4.3 Space and Time Division

23.4.4 Creating and Running Programs on ACM

23.4.5 More Content

23.5 This is Silicon, but Not as We Know It

Chapter 24 Independent Design Tools

24.1 Introduction

24.2 ParaCore Architect

24.2.1 Generating Floating-Point Processing Function Modules

24.2.2 Generating FFT Function Modules

24.2.3 Network-Based Interfaces

24.3 Confluence System Design Language

24.3.1 A Simple Example

24.3.2 More Features

24.3.3 Free Evaluation Version

24.4 Do You Have This Tool?

Chapter 25 Creating Open Source-Based Design Flows

25.1 How to Start an FPGA Design Studio from Scratch

25.2 Development Platform: Linux

25.3 Verification Environment

25.3.1 Icarus Verilog

25.3.2 Dinotrace and GTKWave

25.3.3 Covered Code Coverage Tool

25.3.4 Verilator

25.3.5 Python

25.4 Formal Verification

25.4.1 Open Source Model Checking

25.4.2 Open Source-Based Automated Inference

25.4.3 What is the Real Issue

25.5 Accessing Public IP Components

25.5.1 OpenCores

25.5.2 OVL

25.6 Synthesis and Implementation Tools

25.7 FPGA Development Boards

25.8 Synthesis Materials

Chapter 26 The Future of FPGA Development

26.1 A Concern

26.2 Next-Generation Architectures and Technologies

26.2.1 Billion Transistor-Level Devices

26.2.2 Ultra-Fast I/O

26.2.3 Ultra-Fast Configuration

26.2.4 More Hard IP

26.2.5 Analog and Mixed-Signal Devices

26.2.6 ASMBL and Other Architectures

26.2.7 Different Architectural Granularities

26.2.8 Embedded FPGA Cores in ASIC Structures

26.2.9 Embedded FPNA Cores in ASIC and FPGA Structures or Vice Versa

26.2.10 MRAM-based Devices

26.3 Design Tools

26.4 Expecting the Unexpected

Appendix

Appendix A Introduction to Signal Integrity

Appendix B Submicron Delay Effects

Appendix C Linear Shift Registers

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