Exploring and Grasping Innovation Directions and Development Models of Automotive Chips

Chips are the cornerstone driving the automotive industry towards greater safety, intelligence, efficiency, and comfort. The performance of automotive chips has become one of the key competitive advantages of Chinese smart automotive products and reflects the overall strength of China’s chip industry to some extent. Therefore, understanding the development process and pain points of the entire domestic automotive chip industry chain, clarifying the core demands and optimization directions of key automotive chips, and exploring innovative solutions for chip design and manufacturing processes have become the focal points of industry-wide attention.

For a long time, domestic automotive chips have not developed as expected due to factors such as misalignment in R&D cycles, poor product performance, and insufficient industry accumulation. Firstly, automotive manufacturers generally control the development cycle of vehicle models within three years and determine core components and suppliers in the second year, but it often takes 3-5 years for an automotive chip to go from demand definition to mass production, making it difficult to grasp the timing for introducing domestic chips; secondly, although China’s automotive chips have achieved breakthroughs from 0 to 1 in most areas, high-performance products still lag behind international advanced levels, which may impact the performance of the entire vehicle, leading to fewer domestic chips being used in flagship models that emphasize performance; thirdly, despite continuous progress in design, manufacturing, packaging, and other areas by domestic automotive chip companies in recent years, as newcomers, they lack experience in large-scale production and product failure response, resulting in poor product upgrades and after-sales service, making it difficult to quickly gain the long-term trust of automotive manufacturers.

As autonomous driving evolves to higher levels, the electronic and electrical architecture is accelerating towards a centralized transformation, which poses higher demands on chip performance. In recent years, with the rapid development of automotive intelligence, the electronic and electrical architecture of vehicles is transitioning from distributed to centralized, reducing the number of controllers and integrating some chips into the main chip, thus significantly increasing the functional demands and integration levels of individual chips, which need to meet complex requirements such as multi-core heterogeneity, ultra-high computing power, and ultra-large bandwidth, while also raising higher requirements in terms of information security, functional safety, and real-time performance.

Intelligent driving SOC chips, as the crown jewels, represent the pinnacle of automotive chip performance pursuit. Under the constraints of the electronic and electrical architecture transformation and high-level autonomous driving latency targets (end-to-end latency < 100ms), intelligent driving SOC chips need qualitative improvements in data access volume, data fusion/processing volume, storage space, and functional safety indicators. In addition to performance, the rapid iteration of intelligent driving algorithm architecture also poses challenges for chip flexible adaptation. Previously, both domestic and foreign automotive manufacturers and autonomous driving companies built autonomous driving models based on BEV+Transformer+Occupancy, and most intelligent driving SOC chips were designed based on this, but with the rapid iteration of artificial intelligence algorithms, multi-task end-to-end, visual large models, world models, etc., continuously emerging, the data computing volume and model construction complexity have significantly increased, bringing challenges of flexible expansion and continuous upgrades to SOC chips.

In the future, intelligent driving SOC chips need to be comprehensively optimized from perception, communication, computing, and storage units. In response to the new end-to-end algorithm’s dynamic configuration, complex data, and random access requirements, SOC chips will shift from CPU-centric master-slave computing to ultra-heterogeneous peer-to-peer computing, emphasizing AI computing power, storage capacity, and bandwidth, further optimizing perception (adapting to next-generation sensors), processing (adding DPU units), communication (coordinating with possible distributed data processing), computing (e.g., sparse/approximate computing), storage (e.g., near-memory/in-memory computing), and other units.

Overall, high-end automotive chips will further emphasize extreme performance and flexible adaptation. To meet the perception (large amounts of data, precise collection), communication (large bandwidth, low latency, multi-connection), computing (high performance, strong adaptability), and storage (massive complexity) functions required by intelligent connected vehicles, related automotive chips, especially SOC chips, will emphasize high computing power, configurability, strong integration, and ease of expansion, requiring comprehensive consideration from chip definition, design, manufacturing, and packaging.

Innovations in design and packaging are two breakthrough points for the domestic chip industry to leapfrog. The chip industry chain has achieved a high degree of global division of labor, but most core technologies are held by companies in Europe, America, Japan, and South Korea. With the continuous expansion of domestic terminal demand and the further highlighting of self-controllable demands, the domestic chip industry urgently needs to achieve leapfrog development. EDA tools, IP cores, semiconductor materials, and equipment are the underlying support for the entire chip industry, with high technical barriers, complex processes, and requiring long-term technological accumulation, making rapid breakthroughs impossible; however, in the chip design (defined by usage scenario demands) and packaging testing (relatively labor-intensive industries) stages, Chinese companies have accumulated relatively profound technical experience and domestic capabilities, and are expected to leverage innovative technologies to achieve leapfrog development.

On the design side, domestic chip design is expected to achieve autonomous breakthroughs in CPUs through the RISC-V instruction set architecture. The instruction set is the link connecting software and hardware, compiling system code in applications and operating systems into machine code that can be executed internally by the CPU, completing various calculations, reasoning, judgments, and control tasks, and is a key foundation for the efficient coordination of internal components of the CPU. As the third mainstream instruction set architecture following X86 and ARM, RISC-V has advantages such as open-source, lightweight, and flexible scalability, which helps develop customized chips for entirely new scenario demands and bypass the IP core patent barriers of X86 and ARM, achieving autonomous control of CPUs.

The flexible architecture and good isolation of the RISC-V instruction set have advantages for automotive applications and have begun to be applied in edge node control chips, with the potential to expand to cross-domain/centralized computing in the future. The simple architecture, modular design, open-source acquisition channels, and complete toolchains of the RISC-V instruction set allow its functionalities to be flexibly defined, which aligns very well with automotive demands for embedded chips. Currently, some manufacturers have begun using RISC-V to design automotive chips, such as Renesas Semiconductor, Mobileye, Suzhou Guoxin, Yiswei, and Binary Semiconductor, with these products widely used in edge node controls such as body control, lighting, and TBOX. As its application in smart vehicles is validated, the application scope of the RISC-V instruction set architecture will gradually expand to multi-core functional domain control and centralized heterogeneous computing, and different customized versions can be differentiated for different scenarios to meet diverse passenger needs.

On the packaging side, to further sustain Moore’s Law, advanced packaging solutions continue to iterate, and Chiplet technology has emerged, which, when combined with SiP, can break through process limitations. Chiplet technology is equivalent to modularizing chips, while SiP is system-in-package technology. The essence of the Chiplet-SiP model is to package chiplets and components with different functions and processes together using heterogeneous integration system packaging technology to form a chip that can achieve complete functionality. This model can improve chip performance while reducing design and manufacturing costs, increasing production yield, and shortening iteration cycles, allowing chip manufacturing to partially bypass the limitations of advanced process technology or bring new opportunities for leapfrogging the chip industry.

In the automotive chip field, Chiplet can bring a new development model and is expected to be key to surpassing high-end SOC chips. Currently, there is still a generational gap in process technology between domestic intelligent driving and cockpit SOC chips and internationally leading products. Chiplet offers a possible compromise solution, which can alleviate the current pressure of advanced processes in the domestic market to some extent, aligning with the characteristics of China’s manufacturing lag and mature packaging at this stage. At the same time, Chiplet also brings a shift in the development model, catering to the agile development and rapid iteration needs of automotive chips, but industry-wide discussions on interconnection protocol standardization, system compatibility, packaging solutions, and other issues are still necessary.

In summary, solutions based on RISC-V and Chiplet innovative technologies are important exploratory directions for the domestic development of the next generation of high-performance SOC chips. For the domestic chip industry, enhancing capabilities across the entire industry and all links is a long and arduous task, especially EDA, IP, materials, and equipment still require long-term technological breakthroughs and experience accumulation; at this stage, to address the urgent needs of high-performance automotive chips, innovations in design and packaging can be leveraged as a starting point to explore high-performance SOC chip solutions based on RISC-V architecture and Chiplet technology, promoting the application of domestic chips in vehicles.

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