The Cortex-M3 processor features general-purpose registers R0-R15 along with several special function registers. Registers R0-R12 are 32-bit general-purpose registers used for data operations. However, most 16-bit Thumb instructions can only use R0-R7 (the low register group), while 32-bit Thumb-2 instructions can access all general-purpose registers. The special function registers have predefined functions and must be accessed through specific instructions. R13 serves as the stack pointer (SP). There are two stack pointers (MSP and PSP), but only one can be visible at a time, which is referred to as a “banked” register.
General-Purpose Registers R0-R7
R0-R7 are also known as the low register group. All instructions can access them. They are all 32 bits in length, and their initial values after reset are unpredictable.
General-Purpose Registers R8-R12
R8-R12 are also known as the high register group. This is because only a few 16-bit Thumb instructions can access them, while 32-bit instructions have no restrictions. They are also 32 bits in length, and their initial values after reset are unpredictable.
Stack Pointer R13
R13 is the stack pointer. The CM3 processor core has two stack pointers, thus supporting two stacks. When referencing R13 (or writing as SP), you are referring to the one currently in use; the other must be accessed using special instructions (MRS, MSR instructions). The two stack pointers are:
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Main Stack Pointer (MSP), or written as SP_main. This is the default stack pointer used by the OS kernel, exception service routines, and all application code that requires privileged access.
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Process Stack Pointer (PSP), or written as SP_process. This is used for regular application code (when not in an exception service routine).
It is important to note that not every application must use both stack pointers. Simple applications can suffice with just the MSP. The stack pointer is used to access the stack, and the PUSH and POP instructions default to using SP.
Special Function Registers
The Cortex-M3 also includes several special function registers at the core level, including:
Program Status Register Group (PSRs)
Interrupt Mask Register Group (PRIMASK, FAULTMASK, BASEPRI)
Control Register (CONTROL)
References
Cortex-M3 Authority Guide (Chinese Reference) — Joseph Yiu, translated by Song Yan