Embedded Design Insights: Component Addition Risks

Introduction

In circuit design, neglecting ESD protection and isolation design to reduce costs can lead to serious consequences. This article will explore circuit issues caused by improper component addition and provide practical solutions to ensure the reliability and stability of circuit design.

In circuit design, some neglect ESD protection and isolation design to cut costs, which is not acceptable. To improve reliability and stability, adding protective devices or enhancing driving capability is a common approach. However, if not careful, it may backfire. Adding components to critical circuits can have significant negative impacts:

If the added component affects circuit timing, it is best not to add such devices.
Adding ESD protection devices on the bus clock signal line without proper capacitance control can distort the clock signal waveform, affecting normal communication;
Adding a 22Ω resistor at the bus source end is a common design method, but the overall bus circuit must be considered. If a 22Ω resistor is already placed on the core board, there is no need to add another in series on the bottom board, or it may cause abnormal operation.

Embedded Design Insights: Component Addition Risks Boot Phase Flicker

1. Phenomenon Description

The device exhibits flickering during the BootLoader and kernel stages after power on.

Starting from the software side, delaying the backlight did not completely solve the issue. Observing with an oscilloscope, there was a noticeable delay in the backlight control section.

Next, analyzing from the hardware perspective, the backlight control circuit of the device is shown in Figure 1. Observing with an oscilloscope, when the device powers on, the LCD_BK pin has a high-level pulse, then maintains a low level, and finally transitions to a 20KHz PWM wave.

Embedded Design Insights: Component Addition Risks

Figure 1 Customer’s LCD Backlight Control Circuit

2. Analysis Process

Based on the above phenomena, it can be generally determined to be a power-on timing issue. Measurement shows that VDD_5V powers on earlier than VDD_3V3. When VDD_5V powers on, VDD_3V3 is not powered, the system does not start, and the GPIO is in a high state, so the levels of pins 1 and 2 of Q1 are the same, keeping Q1 off. The LCD_BK signal is pulled high by R3, causing the backlight to turn on, and when the system starts, the GPIO outputs a low level, controlling the backlight to turn off, resulting in the flickering phenomenon.

Checking the backlight driver chip manual, the enable pin high-level threshold is 1.5V, as shown in Figure 2. No level conversion is needed; component Q1 is unnecessary, and 3.3V GPIO can drive it directly.

Embedded Design Insights: Component Addition Risks

Figure 2 Enable Pin High-Level Threshold

3. Solutions

Remove R1, R2, R3, and Q1, and short pins 2 and 3 of Q1. The device will no longer exhibit flickering upon power on.

Embedded Design Insights: Component Addition Risks

TF Card Not Recognized

1. Phenomenon Description

This phenomenon is common when all signal lines of the TF card are equipped with ESD protection devices, with the common issue being incorrect ESD device selection.

2. Analysis Process

Taking the schematic in Figure 3 as an example for analysis.

Figure 3 General Circuit Diagram of TF Card

SD2.0 requires the parasitic capacitance of ESD devices to be less than 9pF. First, check the datasheet of the ESD device (PESD3V3L4UG) and find that its parasitic capacitance can reach up to 28pF (see Figure 4), exceeding the requirement for SD2.0.

Embedded Design Insights: Component Addition Risks

Figure 4 Parasitic Capacitance of PESD3V3L4UG

3. Solutions

Disconnect the ESD device on the CLK line, or replace it with the DT1446-04S-7, which has a parasitic capacitance of only 0.65pF (see Figure 5). After replacement, the TF card is recognized normally.

Embedded Design Insights: Component Addition Risks

Figure 5 Parasitic Capacitance of DT1446-04S-7

Ethernet Matching Resistor

1. Phenomenon Description

There is already a 22Ω source resistor on the Ethernet TX_CLK signal line of the core board, and the customer added a 22Ω matching resistor on the bottom board, causing unstable Ethernet communication.

2. Analysis Process

Inserting the same core board into the evaluation board shows normal Ethernet communication, indicating the bottom board is the cause. Checking the schematic of the bottom board’s Ethernet circuit reveals that the TX_CLK pin is connected in series with a 22Ω matching resistor. The Ethernet reference circuit provided by Zhiyuan Electronics does not include a matching resistor, indicating that the user did not design according to the reference circuit.

Figure 6 New Energy

3. Solutions

Replace the 22Ω resistor on the bottom board with a 0Ω resistor for normal Ethernet communication.

4. Summary

Pay attention to impedance matching for the data lines and control signals of the Ethernet PHY and processor end to avoid signal reflection. It is generally recommended to connect a 22~33Ω resistor in series at the source end in schematic design. However, if the core board already has a matching resistor connected in series at the source end, there is no need to add another matching resistor when designing the bottom board. When developing new products using the core board, it is advisable to refer to the official hardware design reference circuit from Zhiyuan Electronics.