Years ago, a system-on-chip (SoC) with one million transistors was considered a large device, but today, SoCs with up to one billion transistors are common.
Driven by Moore’s Law and the continuous reduction in process sizes, to further meet the performance requirements of applications, the integration of SoC chips has become increasingly high, and system architectures are becoming more complex. As application demands grow richer, SoCs need to integrate more and more different application IPs, and on-chip multi-core interconnected SoCs have become an inevitable trend in their development.
A complex SoC system has various functional module IPs. Taking a digital television SoC chip as an example, it includes a CPU that runs the operating system and applications, a DSP for audio codec processing, a GPU for graphics-related tasks, an NNA for AI image algorithms, as well as some dedicated modules for video codec, post-processing, and video signal modems.
However, with the increasing integration of SoCs and the rapid development of on-chip multi-core interconnected SoCs, the complex combination of multiple different IPs has raised higher demands for on-chip communication, while the complexity of on-chip quality of service (QoS), arbitration, and data flow optimization continues to increase.
To address these issues, Network-on-Chip (NoC) technology has emerged, gradually replacing traditional buses and crossbars, becoming the industry standard for on-chip interconnect.
NoC employs a three-layer communication mechanism of independent transactions, transport, and physical layers to achieve communication between IP modules. In the NoC architecture, each module is connected to an on-chip router, and the data transmitted by the module forms packets that are delivered to the target module through the router, with multiple communication flows multiplexed on these links.
NoC essentially provides a solution for on-chip communication between different IPs or cores within a chip, overcoming the bandwidth bottlenecks of traditional bus networks and crossbars. By adopting an efficient internal communication architecture and flexible interconnection methods, NoC can leverage advantages such as high performance, low power consumption, scalability, and reliability to support the development of emerging fields such as artificial intelligence, the Internet of Things, and autonomous driving.
Against this backdrop and trend,on September 20, 2023, ChuanZhiYiXin Technology and Arteris will jointly hold a technical seminar in Shanghai themed “Harnessing Complex SoC Design with Innovative NoC Technology.”At that time, Professor Ren Pengju, Vice Director of the Institute of Artificial Intelligence and Robotics at Xi’an Jiaotong University, Secretary-General of the Chip Group of the China Artificial Intelligence Industry Development Alliance, Arteris Senior Technical Support Manager Feng Cunrong, and Dr. Shi Xin, Chief Strategy Officer of ChuanZhiYiXin Technology, will deliver keynote speeches on topics related to NoC technology, NoC IP, on-chip networks, and services, sharing key technologies and innovative achievements of NoC in the context of the trend toward high integration of SoCs.
We sincerely invite you to attend the discussion. Scan the QR code below to register in advance (due to limited seats, we will review your registration information as soon as we receive it and send you a confirmation email).
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Agenda Information
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Topic |
Speaker |
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14:00-14:30 |
Registration |
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14:30-14:45 |
Welcome Speech |
ChuanZhiYiXin Technology, Arteris |
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14:45-15:45 |
On-Chip Interconnect Networks — Key Technologies for Multi-Core and Many-Core Processors |
Professor Ren Pengju Xi’an Jiaotong University |
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15:45-16:15 |
Accelerating SoC Creation with FlexNoC Physically-Aware NoC IP |
Feng Cunrong Senior Technical Support Manager, Arteris China |
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16:15-16:45 |
Accelerating Domestic SoC Processor Chip Design — On-Chip Network (NoC) and Services |
Dr. Shi Xin CSO, ChuanZhiYiXin Technology |
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16:45-17:00 |
Q&A |
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Guest and Topic Introduction
Professor Ren Pengju
Professor at Xi’an Jiaotong University, Vice Director of the Institute of Artificial Intelligence and Robotics, Secretary-General of the Chip Group of the China Artificial Intelligence Industry Development Alliance. He obtained his bachelor’s and doctoral degrees from Xi’an Jiaotong University in 2004 and 2012, respectively, and was jointly trained for his doctorate at the Massachusetts Institute of Technology (MIT). His research focuses on novel computing architectures and hybrid-enhanced intelligence for artificial intelligence applications. He has led more than 20 research projects, including the National Nuclear High-Technology Major Project, National Key Research and Development Program (Chief Scientist of Key Special), and National Natural Science Foundation, published one monograph, and over 60 papers in top journals and conferences in the field, including IEEE Trans. Computers, IEEE Trans. CAD, IEEE Trans. NNLs, IEEE Trans. PDS, DAC, CVPR, etc., applied for more than 60 domestic and foreign invention patents, and has been granted 25 patents (including 4 US patents). He has participated in the formulation of more than 10 standards, including those of the International Telecommunication Union and the National Military Standard, and has led and participated in the design and tape-out of 8 dedicated chips (advanced process 5nm). In 2018, he won the First Prize of Natural Science from the Chinese Association of Automation (first contributor) and was awarded as a national-level leading talent and a “Ten Thousand Talents Program” young top talent by the Organization Department of the Central Committee.
Topic: On-Chip Interconnect Networks — Key Technologies for Multi-Core and Many-Core Processors
Abstract:
With the development of integrated circuit semiconductor processes, more and more processing cores will be integrated on a single chip. The emergence of multi-core chips has gradually shifted the focus of traditional processor research from pursuing single-core computing power to researching on-chip communication capabilities, thereby fully organizing and exploiting the parallel processing capabilities of multi-core chips. The design method of on-chip interconnect networks (Network-on-Chip, NoC) provides an exceptionally effective solution for communication interconnects in multi-core chips. From high-performance computers to embedded systems-on-chip (SoC), this design method has been increasingly adopted by many multi-core chips, becoming one of the core contents of SoC technology. This lecture will explain the most basic and critical concepts and knowledge in on-chip network design, focusing on network topology, routing algorithms, flow control, router micro-architecture, and cache coherence communication requirements. It is hoped that through this exchange, more engineers will understand this advanced technology of on-chip networks and inspire everyone to explore more advanced on-chip network design solutions.
Feng Cunrong
Senior Technical Support Manager at Arteris China, engaged in digital IP technical support, chip design, and architecture for many years. Previously, he served as the head of GPU and AI hardware support in Shanghai at Imagination, worked on OPENCL at AMD, and was a chip architecture and design manager at NXP and ST Ericsson, and developed mobile chips at Spreadtrum.
Topic: Accelerating SoC Creation with FlexNoC Physically-Aware NoC IP
Abstract:
Arteris’s FlexNoC 5 is a leading on-chip network interconnect IP widely adopted by top semiconductor and system design teams globally, which can accelerate the development of systems-on-chip. Learn about the latest generation of FlexNoC 5 interconnect and its integrated physically-aware technology, which helps shorten design cycles while reducing interconnect area and power consumption for specific application packaging.
Dr. Shi Xin
Ph.D. from the Institute of Acoustics, Chinese Academy of Sciences, MBA from Peking University, previously held R&D, marketing, and strategic positions at leading international chip design companies such as Samsung Semiconductor, Huawei, Synopsys, ARM, AMD, and Imagination, with over 20 years of experience in IP & EDA, SoC chip design, and management. He understands both upstream technology and downstream ecology and market.
Topic: Accelerating Domestic SoC Processor Chip Design — On-Chip Network (NoC) and Services
Abstract:
As the system performance requirements of systems-on-chip (SoC) continue to rise, NoC (Network on Chip) has become a key technology for multi-core and many-core processors. The domestic market has diverse demands for NoC IP, requiring companies to customize modifications based on different needs. ChuanZhiYiXin Technology will conduct independent research and development based on Arteris products and technologies to accelerate the design of domestic SoC processor chips for the Chinese market.
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