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Recently, blogger @Digital Chat Station revealed that Arm will officially release the next generation “super large core” CPU IP codenamed “Travis” this September.
Previously, at the Computex 2025 conference, it was reported that Travis will achieve a double-digit percentage improvement in IPC (Instructions Per Clock) compared to the existing Cortex-X925, and will include support for Armv9 SME (Scalable Matrix Extension) capabilities.
IPC is a key metric for measuring how many instructions a CPU can execute per clock cycle. Improving IPC means that more calculations can be completed at the same frequency, or equivalent performance can be achieved at a lower frequency, directly leading to reduced power consumption, which is particularly important for mobile phones, laptops, and other terminals.
SME is an instruction set extension aimed at matrix operations, which can accelerate AI inference, image processing, and scientific computing scenarios by handling complex operations like matrix multiplication and accumulation at the hardware level, significantly improving computational efficiency.
Chris Bergey, General Manager of Arm’s Client Products Division, stated that the plan for Travis is to significantly enhance the performance and energy efficiency balance of the “super large core” while maintaining the lightweight characteristics of the existing A-series cores, allowing partners to easily integrate the new IP into next-generation SoC (System on Chip) designs starting in the second half of this year.
In addition to the CPU, Arm also showcased the next-generation GPU IP codenamed “Drage”, aimed at meeting the future mobile gaming and desktop graphics demands.
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