Open source is a trend and a technological movement. While open source software sweeps the globe, open source hardware is also steadily developing. RISC-V, as an open instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC), is currently the hottest open hardware project.In the era of AIoT, product forms are diverse, and application scenarios are varied. From the perspective of efficiency and energy consumption, various industries expect to use Domain-Specific Architectures (DSA) to meet their specific scenario requirements. Currently, the vast majority of instruction set architectures in the chip industry are closed-source, which imposes significant limitations on practical functional expansion and technological innovation. Additionally, regarding various closed-source architectures, from the perspective of the entire industry chain, it has led to issues of redundant design and fragmentation, making optimal allocation of social resources difficult.RISC-V is an industry-wide attempt to address these issues, featuring openness, advancement, standardization, modularity, and scalability in its overall design, giving it a natural advantage in DSA design and effectively meeting the differentiated needs of various fields in the AIoT era.
Allwinner has been quietly cultivating in the chip industry, striving to provide society with more reliable and efficient computing power products. It has also been closely monitoring the growth and development of RISC-V. Based on years of technological accumulation and market understanding, Allwinner has partnered with T-Head to jointly embark on the journey of RISC-V’s industry implementation, aiding the deepening and expansion of various product lines. The T-Head team has years of practical experience in processor design and launched the high-performance RISC-V-based processor Xuantie 910 within a year of its establishment, showcasing its profound technical foundation. As one of the leading companies in the domestic AP-level SoC design industry, Allwinner has deep expertise in chip framework design, interface integration, and high-quality production, with a product ecosystem covering smart hardware, consumer electronics, automotive applications, and industrial interconnects, with annual chip shipments exceeding hundreds of millions. The strong alliance between the two parties greatly ensures the materialization and commercialization of RISC-V.
Currently, Allwinner and T-Head have established a strategic cooperation framework based on the RISC-V instruction set architecture, leveraging each other’s strengths to create a secure and reliable processor technology supply chain from instruction set to IP, chip, and product. Together, they aim to make RISC-V technology accessible to ordinary users.Allwinner Technology adheres to a core value of “customer-centricity,”with the primary goal of the RISC-V products being to satisfy customers and users, bringing value rather than trouble to clients. In addition to providing chips, they also offer two mature software systems: Melis and Tina, enabling Allwinner’s extensive customer base to design, migrate, and apply quickly. Melis, as an RTOS, supports multi-core architectures, dynamic module loading, UI/Net/Multimedia components, with cumulative usage exceeding 500 million, while Tina is a Linux operating system that integrates lightweight AI and GUI, with cumulative usage exceeding 200 million, both highly recognized OS platforms in the industry.Allwinner’s partners are also very confident in RISC-V, as Allwinner Technology’s Vice President Chen Feng stated: “Downstream application developers are very enthusiastic about RISC-V! In the changing times, both pure software developers and integrated hardware-software developers welcome RISC-V very much.”Regarding the construction of the RISC-V ecosystem, Allwinner will maintain a proactive, open, and cooperative attitude to give back to the open-source community. Allwinner Technology’s CTO Ding Ran said: “Although RISC-V is not yet fully mature, we can push forward together and hope to play a certain role and driving force in the development of RISC-V.”
At the beginning of their cooperation, Allwinner and T-Head reached a consensus to develop RISC-V AP-level SoC chips. Through their joint efforts and relentless work, they currently appear competitive in terms of chip area, performance, and power consumption. In 2021, Allwinner plans to launch its first RISC-V SoC, bringing a touch of brightness to the world and injecting new energy into the industry and community!