Thread mode: This mode is active when the processor is reset or exits from an exception. The code in this mode can be either privileged or user code, controlled by CONTROL[0].
Handler mode: This mode is entered when an exception (including interrupts) occurs, and all code in this mode has privileged access.
Privileged access: Complete access rights to processor resources; this access mode is entered after a processor reset; zeroing CONTROL[0] enters user mode.
User access: Access to most system registers is prohibited. Privileged mode can only be returned by entering an exception (interrupt). If the access was user-level before entering the exception, it automatically returns to user-level upon exiting the exception unless CONTROL[0] is modified during the exception.
Operating States
Thumb state (normal execution instruction state) and debug state.
Registers
r0-r12: General-purpose registers, where r8-r12 can only be accessed by 32-bit instructions.
r13 (SP): Stack pointer; can switch between thread stack and main stack in thread mode, but the handler mode only uses the main stack. Only one of the two stacks is visible at any time, and the stack is automatically switched upon entering and exiting an exception.
r14 (LR): Link register, saves the return address of a subroutine or exception (to implement nesting, it must be pushed onto the stack).
r15 (PC): Program counter.
xPSR: Special-purpose program status register.
Exceptions
Steps to enter an exception:
1. The processor automatically pushes the eight registers xPSR, PC, LR, r12, r3~r0 onto the current stack in order.
2. Reads the vector table (if it is a reset interrupt, updates the SP value).
3. Updates the PC value based on the vector table.
4. Loads the instruction at the new PC (steps 2, 3, and 4 occur simultaneously with step 1).
5. Updates LR to EXC_RETURN (EXC_RETURN indicates the mode and stack to return to after exiting the exception).
Steps to Exit an Exception
1. Pop the eight registers that were pushed onto the stack when entering the interrupt based on the stack indicated by EXC_RETURN.
2. Detect which exception to restore based on the [8:0] bits of the just popped IPSR register (at this time, it is in nested interrupt), if it is 0, restore to thread mode.
3. Select the appropriate SP based on EXC_RETURN.
Tail-chaining: If a lower priority interrupt arrives while a higher priority interrupt is currently being executed, this interrupt is temporarily suspended. After the current interrupt execution is completed, it directly enters the suspended interrupt without further stack operations.
Late arrival: If the previous interrupt has not yet entered the execution stage (but the processor state has already been saved), and a higher priority interrupt comes later, the previous interrupt is preempted, and the later high-priority interrupt does not need to save the register state again.
Interrupts
In Cortex-M3, there are two concepts of priority—preemptive priority and response priority. Some refer to response priority as ‘sub-priority’ or ‘secondary priority’; each interrupt source needs to be assigned these two priorities.
Interrupts with high preemptive priority can be responded to during the processing of interrupts with low preemptive priority, meaning interrupt nesting, or high preemptive priority interrupts can nest low preemptive priority interrupts.
When the preemptive priorities of two interrupt sources are the same, these two interrupts will not have nesting relationships. When one interrupt arrives while another interrupt is being processed, the later arriving interrupt will have to wait until the previous interrupt is processed. If both interrupts arrive simultaneously, the interrupt controller decides which one to handle first based on their response priority; if both their preemptive and response priorities are equal, the order in which they are listed in the interrupt table determines which one to handle first.
Source: uTank
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