Disabling Cache for Shared Memory in Cortex-A9
In Xilinx’s Z7000, there are two ARM processors that can exchange information using shared memory. Then, according to a design note from Xilinx, it is recommended to disable the cache for the shared memory area. The fisherman sees this function. Xil_SetTlbAttributes(SHARE_BASE, 0x14de2); I asked CoPilot for the details of this function, and this guy clearly … Read more