As shown in the figure, the green parts are all the v7-A architecture, and the blue ones are the v8-A architecture, basically the green supports both 32 and 64 bits.
Except for A32, which only supports 32 bits. On the right side of each part, for example, the most efficient A15-A73 at the top is the most efficient, followed by the part that focuses on overall efficiency, the middle part is quite efficient, and the bottom part is the best in terms of battery performance.
The latest is also used in the Kirin 980, based on Dynamiq technology, the second-generation high-quality core Cortex A76.
Acore focuses on high performance, and consumer products like smartphones, tablets, set-top boxes, etc., basically all need to use Acore. The development curve of Acore overlaps with the process curve; the latest A76 is based on a 7nm process, A73 is based on a 10nm process, and the earlier A5, A9 mainly used 40nm or 28nm processes.
This is the latest A-series processor released by ARM in 2016, Cortex-A73 supports full-size ARMv8-A architecture, ARMv8-A is ARM’s first processor architecture that supports a 64-bit instruction set, including ARM TrustZone technology, NEON, virtualization, and encryption technology. So whether it is 32-bit or 64-bit, Cortex-A73 can provide the most adaptable mobile application ecosystem development environment. Cortex-A73 includes a 128-bit AMBR 4 ACE interface and ARM’s big.LITTLE system integration interface, manufactured using the most advanced 10nm technology, providing 30% higher sustained processing capability than Cortex-A72, making it very suitable for mobile devices and consumer-grade devices.
The Cortex-A73 processor will gradually cover a series of consumer electronics such as high-end smartphones, tablets, clamshell mobile devices, digital TVs, etc., from our partners.
The big.LITTLE architecture has developed to the latest A76, updating the Dynamiq architecture, with an additional layer of L3 cache outside the core, reducing read and write to external DDR, thus improving performance.
Cortex-A72 was first released in early 2015 and is based on the ARMv8-A architecture. Using TSMC’s 16nm FinFET manufacturing process, Cortex-A72 can achieve performance independently on chips or be paired with the Cortex-A53 processor to form an ARM big.LITTLE configuration with ARM CoreLinkTMCCI cache coherence interconnect, further improving energy efficiency. Under the same mobile device battery life constraints, Cortex-A72 can provide 3.5 times the performance of devices based on Cortex-A15, and about 1.8 times the performance improvement compared to Cortex-A57, demonstrating excellent overall power consumption efficiency.
Cortex-A72 is currently one of the most widely used processors based on the ARMv8-A architecture, and its main application markets include high-end smartphones, large-screen mobile devices, enterprise network devices, servers, wireless base stations, and digital TVs.
Cortex-A57 is the flagship CPU of ARM’s CPU product series designed for the starting points of 2013, 2014, and 2015. It is also the first ARM CPU to adopt the 64-bit ARMv8-A architecture and maintains full backward compatibility with the ARMv7 architecture through the Aarch32 execution state. In addition to the advantages of the ARMv8 architecture, Cortex-A57 also improves single-clock cycle performance, surpassing the high-performance Cortex-A15 CPU by 20% to 40%.
It also improves the design of the second-level cache and other components of the memory system, greatly enhancing energy efficiency. Cortex-A57 will provide ultra-high performance for mobile systems, and with the help of big.LITTLE, SoC can achieve this with very low average power consumption. Its main targets are mid-to-high-end computers, tablets, and server products.
Cortex-A53 also adopts the ARMv8-A architecture and can support both 32-bit ARMv7 code and 64-bit AArch64 execution state. The A53 architecture is characterized by reduced power consumption and improved energy efficiency. Its target is to ensure that under the 28nm HPM manufacturing process, the power consumption of a single core does not exceed 0.13W.
It provides better performance than the Cortex-A7 processor’s power efficiency and can serve as a standalone main application processor or be paired with the Cortex-A57 processor to form a big.LITTLE configuration. At the same frequency, Cortex-A53 can provide higher performance than Cortex-A9. Its main targets are mid-to-high-end computers, tablets, set-top boxes, and digital TVs.
Cortex-A35 is a low-power CPU designed based on the ARMv8-A 64-bit architecture, aimed at replacing the previous 32-bit Cortex-A7 and Cortex-A5 cores. It adopts a similar in-order dual-issue design as A53/A7 while incorporating some new features from A72, and has redesigned the instruction prefetch unit in the front end to enhance branch prediction accuracy. In addition, A35 also adopts the cache and memory architecture of A53, configurable with 8-64KB Level 1 instruction and data cache, 128KB-1MB Level 2 cache, integrates NEON/FP units, improves storage performance, supports complete pipelined double-precision multiplication, and equips both CPU cores and NEON pipelines with hardware retention states (independent power domains) to enhance power management efficiency. Under the same process and frequency, A35’s power consumption is about 10% lower than A7, while performance improves by 6-40%.
Compared to A53, it can retain 80-100% of performance, but power consumption is reduced by 32%, and area shrinks by 25%, improving energy efficiency by 25%. A35 can also be paired with larger cores such as A53, A57, and A72 to form a big.LITTLE hybrid architecture system, further enhancing system energy efficiency. Its main positioning is in low-power low-end smartphones, wearables, and IoT fields.
This is the only 32-bit (ARMv7-A) architecture processor in ARM’s new generation architecture, but A32 is like a 32-bit version of A35, with a clear goal of further controlling power consumption based on the already impressive performance of A35. The A32 architecture focuses on chip area, power consumption control, and energy efficiency, remaining at 32 bits (ARMv7-A instruction set), with the instruction prefetch unit redesigned for efficiency, and both Level 1 and Level 2 caches, floating-point, and DSP operation performance improved for speed, introducing new power management features. It supports TrustZone secure encryption, NEON SIMD instruction set, DSP/SIMD extensions, VFPv4 floating-point computation, virtual hardware, etc.
A32 can provide performance equivalent to A35 at 32 bits. But with lower power consumption, its performance efficiency (performance per unit of power) is 10% higher than A35, 30% higher than A5, and 25% higher than A7. A35 can achieve 80-100% performance of A53 by increasing frequency, meaning A32 can also achieve the same performance level at 32 bits, with chip area only 68% of A53 and power consumption only 61% of A53.
In 64-bit mode, A35 has the strength to replace the A53 architecture, while in 32-bit mode, A32 already dominates all others, and compared to the 64-bit A35 architecture, the 32-bit A32 is more suitable for use in wearable devices and IoT products.
A17 is still based on the 32-bit ARMv7-A instruction set, initially adopting a 28nm process, later evolving to 20nm. The essential architecture is the same as A12, which is dual-width and out-of-order issuing, only improving external interconnects, introducing a new coherence bus AMBA4 ACE, which can connect to memory controllers faster, thereby improving performance and energy efficiency.
Thanks to this new bus, A17 can support complete memory consistency operations for multi-core SoCs, participate in big.LITTLE dual architecture hybrid solutions, and under specific frequency, process, and memory conditions, A17’s performance improves by about 40% compared to A12. In certain specific environments, A17’s performance can already match that of A15, but with lower power consumption and higher energy efficiency. Although it is named above Cortex-A15, its positioning is mid-range, not high-end.
Cortex-A15 was first released in 2010, based on the 32-bit ARMv7-A architecture. A15 and A9 both support out-of-order execution, but Cortex-A15 has (twice) the instruction issue ports and execution resources, 50% higher instruction decoding capability, stronger dynamic branch prediction capability (using multi-level branch table cache), and stronger instruction fetch bandwidth (128 bit vs 64 bit), all of which enable A15’s pipeline execution to be more efficient. Additionally, A15 adopts the VFPv4 floating-point unit design, capable of executing FMA instructions and hardware division instructions, whereas A9’s peak vector floating-point performance is basically only half that of A15.
Cortex-A15 processors can be applied in smartphones, tablets, mobile computing, high-end digital appliances, servers, and wireless infrastructure devices.
ARM Cortex-A9 adopts the ARMv7-A architecture, and currently, most of the quad-core processors we see belong to the Cortex-A9 series. The Cortex-A9 processor is designed to create the most advanced, efficient, dynamically variable length, multi-instruction execution superscalar architecture, providing an 8-stage pipeline processor that executes using out-of-order speculation, with the functionality required by a wide range of consumer, networking, enterprise, and mobile applications, capable of combining high performance and high energy efficiency.
The Cortex-A9 microarchitecture can be used for scalable multi-core processors (Cortex-A9 MPCore multi-core processors) or more traditional processors (Cortex-A9 single-core processors). Scalable multi-core processors and single-core processors support 16, 32, or 64KB 4-way associative L1 cache configurations, and for optional L2 cache controllers, support up to 8MB of L2 cache configurations, offering extremely high flexibility, suitable for specific application fields and markets.
The ARM Cortex-A8 processor, based on the ARMv7-A architecture, is currently the most common product used in single-core smartphones. The Cortex-A8 processor is the first product based on the ARMv7 architecture, capable of increasing speed from 600MHz to over 1GHz. The Cortex-A8 processor can meet the power optimization requirements for mobile devices that need to operate below 300mW; and the performance optimization requirements for consumer applications requiring 2000 Dhrystone MIPS.
The Cortex-A8 high-performance processor is now very mature, providing reliable high-performance solutions from smartphones to netbooks, DTV, printers, and automotive infotainment.
The Cortex-A7 adopts the ARMv7-A architecture, characterized by providing excellent low-power performance while ensuring performance. The Cortex-A7 processor’s architecture and functionality are identical to the Cortex-A15 processor, except that the Cortex-A7 processor’s microarchitecture focuses on providing optimal energy efficiency, allowing these two processors to work together in a big.LITTLE configuration, providing the ultimate combination of high performance and ultra-low power consumption. A single Cortex-A7 processor’s energy efficiency is five times that of the Cortex-A8 processor, with a 50% performance improvement, while its size is only one-fifth of the latter.
The Cortex-A5 processor is also based on the ARMv7-A architecture and is the most efficient and cost-effective processor, capable of providing the most basic Internet access to the widest range of devices. The Cortex-A5 processor is fully compatible in terms of instructions and functionality with higher-performance Cortex-A8, Cortex-A9, and Cortex-A15 processors – even at the operating system level. The Cortex-A5 processor also maintains backward application compatibility with classic ARM processors (including ARM926EJ-S, ARM1176JZ-S). Its positioning is for entry-level smartphones, low-cost phones, smart mobile devices, and basic industrial devices.
Original link:
https://www.cnblogs.com/craze-ic/p/11052228.html
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