100 Common Abbreviations in IC Design

English Abbreviation

Full English Name

Chinese Explanation

ADC

Analog to Digital Converter

Analog signal to digital signal conversion circuit

AHB

Advanced High Performance Bus

A bus specification launched by ARM for high-performance modules (such as CPU, DMA, and DSP) connections

APR

Auto Place and Route

Automatic layout and routing, a main process in digital backend layout implementation

ARM

Acorn RISC Machine

The ARM company in the UK, commonly used in mobile chips or processors, now low-power designs generally adopt ARM CPU

ASIC

Application-Specific Integrated Circuit

Application-specific integrated circuit, mainstream design process for chip design companies

ATPG

Auto Test Pattern Generator

Test vector automatic generation tool, a common process in DFT

AXI

Advanced eXtensible Interface

A bus specification launched by ARM

BE

Back End

Backend, referring to the backend design process in IC design

BIST

Built-In Self-Test

Built-in testing system, a common process in DFT

CAD

Computer-Aided Design

Computer-aided design, also a department in IC design companies that specializes in providing software automation

CDC

Clock Domain Crossing

Asynchronous clock timing checks, an important step in digital design

COVERAGE

Coverage

A common term in digital verification, mainly including code coverage and functional coverage

CPLD

Complex Programmable Logic Device

Complex programmable device, similar to FPGA

CTS

Clock Tree Synthesis

Clock tree synthesis, an important process in digital backend implementation

DAC

Digital to Analog Converter

Digital signal to analog signal conversion circuit

DC

Design Compiler

A digital synthesis tool from Synopsys

DFT

Design for Test

A design method adopted to enhance chip testability, an important step in the digital IC process

DMA

Direct Memory Access

Direct memory access

DRAM

Dynamic Random Access Memory

Dynamic random-access memory, the most common system memory

DRC

Design Rule Check

Check whether the generated layout meets the design rules provided by the foundry, such as width, spacing, area, etc.

DSP

Digital Signal Processing

Digital signal processing module, often used in algorithm implementation by IC design companies

DUT

Design Under Test

Design module to be tested

DUV

Design Under Verification

Similar meaning to DUT

ECO

Engineering Change Order

In the later stages of a project, modifications to the chip design can only be made at the gate level

EDA

Electronic Design Automation

Electronic design automation, many EDA tools are required in the IC design process

EEPROM

Electrically Erasable Programmable Read-Only Memory

Electrically erasable read-only memory

ERC

Electronic Rule Check

Check whether the IC design meets electrical rules after layout

FE

Front End

Frontend, the frontend design process in digital IC design

FLASH

Flash EEPROM Memory

Flash memory, which combines the fast data reading characteristics of RAM with the erasable and non-volatile nature of EEPROM.

FM

Formal

Formal verification, comparing netlists with Verilog

Foundry

Refers to the foundry business of chip manufacturing, responsible for producing completed chip designs

FPGA

Field Programmable Gate Array

Field-programmable gate array, corresponding to the ASIC process

FSDB

A common waveform file format in digital IC design

FSM

Finite State Machine

Finite state machine in digital logic design

FULLCHIP

Fullchip Level

Commonly used in digital frontend design and verification, referring to system-level and chip-level

GDSII

File format for layout

GLS

Gate Level Simulation

Refers to gate-level simulation in digital verification

GPIO

General Purpose Input Output

General input/output, bus expander

HDMI

High Definition Multimedia Interface

High-definition multimedia interface, a digital video/audio interface technology specification

I2C

Inter-Integrated Circuit

IIC is a commonly used multi-directional control bus, simple, with only two lines

IC

Integrated Circuit

Integrated circuit

ICC

IC Compiler

A software from Synopsys for automatic layout and routing, widely used by many companies

IEEE

Institute of Electrical and Electronics Engineers

The Institute of Electrical and Electronics Engineers

INNOVUS

A digital layout implementation tool from Cadence

IP

Intellectual Property

Intellectual property, in digital IC design, the smallest design module is generally referred to as IP

JTAG

Joint Test Action Group

Joint Test Action Group, an international standard testing protocol, commonly used for chip testing

Layout

Layout, referring to the final layout generated for the chip, similar to design blueprints in the construction industry

LPS

Low Power Simulation

Low power simulation, commonly used in low power design verification

LSI

Large-Scale Integrated Circuit

Large-scale integrated circuit

LUT

Look Up Table

Lookup table, used to store some data, essentially a RAM

LVS

Layout versus Schematic

Check the consistency between the layout and the schematic after transforming to layout

MCU

Microcontroller Unit

Microcontroller, main control module

MIPI

Mobile Industry Processor Interface

Mobile industry processor interface, an open standard and specification for mobile application processors

Modelsim

A digital frontend simulation tool from Mentor, also known as QUESTASIM

MPW

Multiple Project Wafer

Multi-project wafer, refers to placing different chips of the same process on the same wafer, an effective way for small companies to save costs

MSB

Most Significant Bit

The most significant bit of a multi-bit data, corresponding concept is LSB

NCSIM

A digital frontend simulation tool from Cadence

NDR

Non-Default Route

Non-default wiring rules, an important concept in layout implementation

Netlist

Gate-level netlist, generally a netlist file generated from RTL Code using synthesis tools

NFC

Near Field Communication

A wireless communication technology for short distances

OCP

Open Core Protocol

An efficient, bus-independent, configurable, and highly scalable interface protocol

PAD

Refers to the input/output ports of a chip

PBA

Path-Based Analyze

Path-based timing analysis

PCIe

Peripheral Component Interconnect Express

A standard for peripheral component interconnect, a common bus standard

PD

Physical Design

Physical design, generally refers to the layout design of the digital backend

PERL

A commonly used scripting language in digital IC design, very suitable for text processing

PLL

Phase Locked Loop

Phase-locked loop, commonly used in clock frequency multiplication circuits to generate clock clock

PT

Prime Time

A static timing analysis tool from Synopsys

PV

Physical Verification

Physical verification, necessary verification after digital layout implementation

Python

A commonly used scripting language, now widely used in artificial intelligence and very popular

R&D

Research and Design

R&D center

RAM

Random Access Memory

Random access memory

REGRESSION

Regression testing, simply put, running all test cases repeatedly until there are no errors for a period of time

RF

Radiation Frequency

Transmission frequency, radio frequency circuit

RISC

Reduced Instruction Set Computer

Used in CPU, a reduced instruction set

ROM

Read Only Memory

Read-only memory with non-volatility.

RTL

Register Transfer Level

Register transfer level, often refers to levels described using Verilog

Shell

A commonly used scripting language in digital IC design, closely integrated with Linux

SI

Signal Integrity

Signal integrity

signoff

Acceptance mechanism, acceptance criteria

SoC

System on Chip

System on chip, generally refers to larger chips, mostly containing CPU/MCU and others

SPEC

Specification

Specification, every engineer in each position must write the corresponding spec

SPI

Serial Peripheral Interface

A serial peripheral interface, a high-speed, full-duplex, synchronous communication bus

SRAM

Static Random Access Memory

Static random-access memory

STA

Static Timing Analysis

Static timing analysis, an important part of the digital IC design process

SV

SystemVerilog

Mainstream digital verification language

Tapout

Tape Out

Sending the final layout file to the foundry for production

TCL

Tool Command Language

Tool command language. A commonly used scripting language in digital backend design

tessent

A DFT tool from Mentor, with a high market share

Testbench

Test platform, a platform used for testing in digital verification

TTL

Transistor-Transistor Logic

TTL voltage standard, stipulates that +5V is equivalent to logic 1, and 0V is equivalent to logic 0

UART

Universal Asynchronous Receiver/Transmitter

A common IP module, a universal asynchronous transceiver

USB

Universal Serial Bus

A high-speed bus protocol for connecting peripherals

UVM

Universal Verification Methodology

A mainstream digital verification methodology based on SystemVerilog

VCD

Value Change Dump

A common waveform file format, detailed information but larger file size

VCS

A digital frontend simulation tool from Synopsys

Verdi

A digital frontend debugging tool from Synopsys

VHDL

VHSIC (Very High Speed IC) Hardware Description Language

A hardware description language, similar to Verilog, but now not many companies use it

Vivado

Vivado

An integrated design environment released by Xilinx for FPGA in 2012

VLSI

Very-Large-Scale Integrated Circuit

Ultra-large-scale integrated circuit